Patents by Inventor Katsuhiro Shimohigashi

Katsuhiro Shimohigashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6864559
    Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: March 8, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
  • Patent number: 6740958
    Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.
    Type: Grant
    Filed: April 4, 2002
    Date of Patent: May 25, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
  • Publication number: 20030178699
    Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.
    Type: Application
    Filed: March 4, 2003
    Publication date: September 25, 2003
    Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
  • Publication number: 20020153591
    Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.
    Type: Application
    Filed: April 4, 2002
    Publication date: October 24, 2002
    Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
  • Patent number: 6208010
    Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.
    Type: Grant
    Filed: December 18, 1995
    Date of Patent: March 27, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
  • Patent number: 5808951
    Abstract: A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.
    Type: Grant
    Filed: September 17, 1997
    Date of Patent: September 15, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Katsuhiro Shimohigashi, Hiroo Masuda, Kunihiko Ikuzaki, Hiroshi Kawamoto
  • Patent number: 5732037
    Abstract: A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.
    Type: Grant
    Filed: May 23, 1995
    Date of Patent: March 24, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Katsuhiro Shimohigashi, Hiroo Masuda, Kunihiko Ikuzaki, Hiroshi Kawamoto
  • Patent number: 5689457
    Abstract: A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.
    Type: Grant
    Filed: March 6, 1996
    Date of Patent: November 18, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Katsuhiro Shimohigashi, Hiroo Masuda, Kunihiko Ikuzaki, Hiroshi Kawamoto
  • Patent number: 5629898
    Abstract: A period pulse corresponding to the shortest information retention time of those of dynamic memory cells is counted to form a refresh address to be assigned to a plurality of word lines. A carry signal outputted from the refresh address counter is divided by a divider. For each of said plurality of word lines assigned with the refresh address, one of a short period corresponding to an output pulse of a timer or a long period corresponding to the divided pulse from the divider is stored in a storage circuit as refresh time setting information. A memory cell refresh operation to be performed by the refresh address is made valid or invalid for each word line according to the refresh time setting information stored in the storage circuit and the refresh time setting information itself is made invalid by the output pulse of the divider.
    Type: Grant
    Filed: February 29, 1996
    Date of Patent: May 13, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Youji Idei, Katsuhiro Shimohigashi, Masakazu Aoki, Hiromasa Noda, Katsuyuki Sato, Hidetoshi Iwai, Makoto Saeki, Jun Murata, Yoshitaka Tadaki, Toshihiro Sekiguchi, Osamu Tsuchiya
  • Patent number: 5550781
    Abstract: A memory cartridge having a plurality of dynamic memory units includes an access conversion circuit which converts a static access signal into its inverted signal and an access control circuit which controllably switches between a signal for refreshing each dynamic unit and a signal for external access. The memory cartridge also includes a power switching circuit which switches power from an internal power supply to an external power supply when the memory cartridge is mounted to an external device.
    Type: Grant
    Filed: January 31, 1995
    Date of Patent: August 27, 1996
    Assignees: Hitachi Maxell, Ltd., Hitachi, Ltd
    Inventors: Ken Sugawara, Shigeru Sakairi, Mikio Matoba, Toshio Sasaki, Katsuhiro Shimohigashi, Katsutaka Kimura
  • Patent number: 5497023
    Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.
    Type: Grant
    Filed: December 8, 1994
    Date of Patent: March 5, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikasu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
  • Patent number: 5467314
    Abstract: In an address multiplexed dynamic random access memory (RAM) which has both a normal operation mode and a test mode capability, the test mode is initiated in response to particular signal level combinations of both the row address strobe (RAS) and column address strobe (CAS) signals and the write enable (WE) signal. Since the signal level combinations employed in connection with implementing the test mode are unused in the normal operating mode of the dynamic RAM, additional external terminals are unneeded. This dynamic RAM employs multiplexing circuitry on both the input side as well as on the output side of the dynamic RAM, which multiplexing circuitry is controlled during normal operation by select signals from a decoder and during the test mode by a test signal which allows accessing of data at all of the common complementary data lines by the testing circuitry so as to determine whether there is consistency or inconsistency of the data being read out for testing.
    Type: Grant
    Filed: July 18, 1994
    Date of Patent: November 14, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Kazuyuki Miyazawa, Katsuhiro Shimohigashi, Jun Etoh, Katsutaka Kimura
  • Patent number: 5448520
    Abstract: A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed irk the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.
    Type: Grant
    Filed: September 15, 1994
    Date of Patent: September 5, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Katsuhiro Shimohigashi, Hiroo Masuda, Kunihiko Ikuzaki, Hiroshi Kawamoto
  • Patent number: 5430681
    Abstract: A memory cartridge having a plurality of dynamic memory units includes an access conversion circuit which converts a static access signal into its inverted signal and an access control circuit which controllably switches between a signal for refreshing each dynamic unit and a signal for external access. The memory cartridge also includes a power switching circuit which switches power from an internal power supply to an external power supply when the memory cartridge is mounted to an external device.
    Type: Grant
    Filed: July 5, 1994
    Date of Patent: July 4, 1995
    Assignees: Hitachi Maxell, Ltd., Hitachi, Ltd.
    Inventors: Ken Sugawara, Shigeru Sakairi, Mikio Matoba, Toshio Sasaki, Katsuhiro Shimohigashi, Katsutaka Kimura
  • Patent number: 5386135
    Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.
    Type: Grant
    Filed: April 12, 1994
    Date of Patent: January 31, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
  • Patent number: 5381531
    Abstract: An instruction fetch unit (640) of a data processor (610) capable of simultaneous execution of two instructions fetches a first and a second instruction from a memory (620) in one cycle. The first and the second instruction thus fetched are set in a first and a second register (641, 642) before being decoded in a first and a second instruction decoder (644, 645). Comparators (131, 132) compares data on the destination field of the first instruction with data on the source field of the second instruction. When both the data are inconsistent, a parallel operation control unit (646) permits the first and the second instruction execution unit (651, 652) under the first and the second instruction to execute the two instructions in response to the outputs of the comparators (131, 132). When both the data are consistent, the parallel operation control unit (646) inhibits the parallel execution.
    Type: Grant
    Filed: July 9, 1991
    Date of Patent: January 10, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Hanawa, Tadahiko Nishimukai, Makoto Suzuki, Katsuhiro Shimohigashi
  • Patent number: 5365478
    Abstract: A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.
    Type: Grant
    Filed: February 9, 1994
    Date of Patent: November 15, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Katsuhiro Shimohigashi, Hiroo Masuda, Kunihiko Ikuzaki, Hiroshi Kawamoto
  • Patent number: 5331596
    Abstract: An address multiplexed dynamic random access memory (RAM) which has both a normal operation mode and a test mode capability is provided. The test mode is initiated in response to particular signal level combinations of both the row address strobe (RAS) and column address strobe (CAS) signals and the write enable (WE) signal. Since the signal level combinations employed in connection with implementing the test mode are unused in the normal operating mode of the dynamic RAM, additional external terminals are unneeded. This dynamic RAM employs multiplexing circuitry on both the input side as well as on the output side of the dynamic RAM, which multiplexing circuitry is controlled during normal operation by select signals from a decoder and during the test mode by a test signal which allows accessing of data at all of the common complementary data lines by the testing circuitry so as to determine whether there is consistency or inconsistency of the data being read out for testing.
    Type: Grant
    Filed: May 26, 1992
    Date of Patent: July 19, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Kazuyuki Miyazawa, Katsuhiro Shimohigashi, Jun Etoh, Katsutaka Kimura
  • Patent number: 5324982
    Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.
    Type: Grant
    Filed: October 2, 1991
    Date of Patent: June 28, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
  • Patent number: 5253197
    Abstract: In a first embodiment of a CAM (Content Addressable Memory) or cache memory of the present invention disclosed herein, comparing information stored in a memory cell with comparison input information is accomplished in a comparison circuit without first converting a readout current from the memory cell into voltage information. In another embodiment, a matching detection between first stored information outputted from a first memory cell array and second stored information outputted from a second memory cell array is accomplished by an integrally formed sensing and matching detection circuit which is characterized as having both sensing and matching detection capabilities. That is, the sensing and matching detection circuit senses both stored information and thereafter detects matching based on a sensing result.
    Type: Grant
    Filed: September 11, 1990
    Date of Patent: October 12, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Suzuki, Suguru Tachibana, Hisayuki Higuchi, Katsuhiro Shimohigashi, Takehisa Hayashi, Makoto Hanawa, Tadahiko Nishimukai