Abstract: On a surface of a semiconductor substrate within a device forming region, a MOS transistor including a gate electrode, gate oxide film and source•drain is formed. An insulating layer is formed on the surface of the semiconductor substrate. In an opening of the insulating layer above the source•drain, a tungsten plug is formed. At a dicing line portion, the insulating layer has a trench portion. The trench portion is formed to surround the device forming region. A tungsten street having a top surface continuous to the top surface of the insulating layer is formed in the trench. By this semiconductor device, short-circuit between bonding pads and the like can be prevented, and the reliability can be improved.

Abstract: On a surface of a semiconductor substrate within a device forming region, a MOS transistor including a gate electrode, gate oxide film and source.cndot.drain is formed. An insulating layer is formed on the surface of the semiconductor substrate. In an opening of the insulating layer above the source.cndot.drain, a tungsten plug is formed. At a dicing line portion, the insulating layer has a trench portion. The trench portion is formed to surround the device forming region. A tungsten street having a top surface continuous to the top surface of the insulating layer is formed in the trench. By this semiconductor device, short-circuit between bonding pads and the like can be prevented, and the reliability can be improved.

Abstract: A semiconductor memory device comprises a capacitor and a transistor formed on a main surface of a semiconductor substrate and a buried layer of high impurity concentration formed in the substrate, wherein the buried layer has the same conductivity type as that of the substrate and is formed shallow under the capacitor and deep under the transistor.

Abstract: A lower electrode of a capacitor for use in a semiconductor device includes a first semiconductor layer having a predetermined impurity concentration and a second semiconductor layer having an impurity concentration higher than that of the first semiconductor layer. As a result, intensification of an electric field at an end portion of the capacitor can be reduced. In addition, a word line is formed of a buffer layer and a main conductor layer to reduce a parasitic capacitance between the lower electrode of the capacitor and the word line.

Abstract: A natural oxide film formed on an impurity region exposed in the formation of a through-hole is reduced by a titanium silicide layer formed by a CVD method. The natural oxide film is reduced at the time of forming the titanium silicide film. The silicon used for forming the titanium silicide film is supplied from a gas including silicon. Therefore, the titanium silicide film can be prevented from intruding excessively into the impurity region.

Abstract: There is disclosed a semiconductor device including a plurality of P well regions (4) and a P well region (41) insulated from each other by a plurality of trench isolating layers (10) formed regularly in predetermined spaced relation with each other and having the same depth. The outermost P well region (41) isolatedly formed externally of an outermost trench isolating layer (10A) is made as deep as the trench isolating layers (10) and, accordingly, is made deeper than the P well regions (4) except the outermost P well region (41). This provides for the alleviation of the electric field concentration generated in the bottom edge of the outermost isolating layer of trench structure, thereby achieving the semiconductor device having an improved device breakdown voltage and a method of fabricating the same.

Abstract: A complementary field effect element develops an intensified latch-up preventive property even if the distance between the emitters of parasitic transistors is short, and a method of producing the same are disclosed. The complementary field effect element includes a high concentration impurity layer (16) formed by ion implantation in the boundary region between a P-well (2) and an N-well (3) which are formed adjacent each other on the main surface of a semiconductor substrate (1). Therefore, carriers passing through the boundary region between the P-well (2) and the N-well (3) are decreased, so that even if the distance between the emitters (4, 5) of parasitic transistors is short, there is obtained an intensified latch-up preventive property.

Abstract: A thick isolation oxide film is selectively formed on a surface of a silicon substrate so as to isolate an element formation region. Ions are implanted into a region in silicon substrate through the thick isolation oxide film. Thus, retrograde wells, having impurity concentration peak positions are formed in the region of silicon substrate positioned under the isolation oxide film. Then, an upper part of the isolation oxide film is removed away to form an isolation oxide film with a reduced thickness. Isolation oxide film has a reduced isolation length L. Thus, a semiconductor device is provided, which permits restriction of the narrow channel effect and the substrate biasing effect when the size of elements is reduced.

Abstract: The present invention provides a method for removing a natural gas film or contaminant adhering on a surface of a silicon semiconductor substrate. The semiconductor substrate having the natural oxide film or contaminant adhered thereon is placed in a chamber. Then, a HCl gas is introduced into the chamber. The semiconductor substrate is heated at a temperature in the range of 200.degree..about.700.degree. C., while ultraviolet rays are irradiated into the chamber. According to the method, the reaction of the natural oxide with HCl gas is promoted by a synergistic effect of light and heat energy. Therefore, the natural oxide film or contaminant can be removed at a lower temperature with the help of the light energy.

Abstract: A method of manufacturing a semiconductor memory device having a peripheral circuit portion, the operating voltage of which is relatively high and a memory array portion, the operating voltage of which is relatively low comprises the steps of forming an inversion preventing layer on the peripheral circuit portion, forming an oxide layer for isolation between-devices adjacent thereto, forming on the memory array portion the inversion preventing layer, the impurity concentration of which is higher than that of the peripheral circuit portion and forming the oxide layer on the peripheral circuit portion at the same time that the oxide layer for isolation between devices is formed adjacent thereto.

Abstract: A semiconductor device for element isolation comprises a semiconductor substrate having an impurity region of a first conductivity type whose impurity concentration attains the maximum at a predetermined depth from the surface in the depth direction, a trench formed to a predetermined depth in the impurity region of the first conductivity type, and an impurity diffusion region of the first conductivity type formed in the trench with an oxide film interposed and having only its bottom portion connected to the impurity region of the first conductivity type of the semiconductor substrate. In the semiconductor device, a uniform P.sup.+ high concentration region is substantially formed in a bottom portion of an isolation region, so that an isolation threshold value is not affected.

Abstract: A micro MIS type FET comprises first conductivity type source/drain regions formed in a surface of a semiconductor layer mutually spaced apart by a distance of less than 2 .mu.m, a second conductivity type channel layer having an impurity concentration of less than 1.times.10.sup.16 /cm.sup.3 formed between the source/drain regions to have a depth less than depths of the source/drain regions, and a second conductivity type threshold voltage control region having an impurity concentration of more than 1.times.10.sup.17 /cm.sup.3 beneath the channel layer.

Abstract: A semiconductor device comprises a P-type semiconductor substrate having a major surface, an insulating film formed on the major surface of the semiconductor substrate, a first polycrystalline silicon layer formed on the insulating film, an n.sup.+ diffused layer formed on the substrate and adjacent to an end portion of the first polycrystalline silicon layer, and a side wall formed on the end portion of the first polycrystalline silicon layer and formed of a second polycrystalline silicon layer for connecting the end portion of the first polycrystalline silicon layer with the n.sup.+ diffused layer.

Abstract: A lower electrode of a capacitor for use in a semiconductor device includes a first semiconductor layer having a predetermined impurity concentration and a second semiconductor layer having an impurity concentration higher than that of the first semiconductor layer. As a result, intensification of an electric field at an end portion of the capacitor can be reduced. In addition, a word line is formed of a buffer layer and a main conductor layer to reduce a parasitic capacitance between the lower electrode of the capacitor and the word line.

Abstract: A method of and an apparatus for removing a naturally grown oxide film and contaminants on the surface of a semiconductor substrate and then forming a thin film on the cleaned surface. The semiconductor substrate is placed in a pretreatment chamber and then hydrogen chloride gas is introduced into the chamber. Then, the semiconductor substrate is heated at a temperature between 200.degree..about.700.degree. C. and the surface of the semiconductor substrate is irradiated with ultraviolet rays, whereby the naturally grown oxide film and other contaminants on the semiconductor substrate can be removed. Then, a thin film is formed on the cleaned surface of the semiconductor substrate by a CVD method or a sputter method. According to this method, the naturally oxide film and other contaminants can be removed from the surface of the semiconductor substrate at a low temperature and the thin film can be formed on the cleaned surface.

Abstract: A semiconductor device has an upper well of a first conductivity type formed from the surface of an active region separated by an isolation oxide film at the surface of a semiconductor substrate to a predetermined depth. A first conductivity type layer of high concentration is formed along the entire region of an active region to enclose the bottom of the upper well of the first conductivity type. A lower well of the first conductivity type of a predetermined thickness is formed as a buried layer to enclose the bottom of the first conductivity type layer of high concentration. According to this structure, the spreadout of impurities into the active region due to diffusion at the time of thermal treatment is suppressed.

Abstract: A micro MIS type FET comprises first conductivity type source/drain regions formed in a surface of a semiconductor layer mutually spaced apart by a distance of less than 2 .mu.m, a second conductivity type channel layer having an impurity concentration of less than 1.times.10.sup.16 /cm.sup.3 formed between the source/drain regions to have a depth less than depths of the source/drain regions, and a second conductivity type threshold voltage control region having an impurity concentration of more than 1.times.10.sup.17 /cm.sup.3 beneath the channel layer.

Abstract: A semiconductor device has an upper well of a first conductivity type formed from the surface of an active region separated by an isolation oxide film at the surface of a semiconductor substrate to a predetermined depth. A first conductivity type layer of high concentration is formed along the entire region of an active region to enclose the bottom of the upper well of the first conductivity type. A lower well of the first conductivity type of a predetermined thickness is formed as a buried layer to enclose the bottom of the first conductivity type layer of high concentration. According to this structure, the spreadout of impurities into the active region due to diffusion at the time of thermal treatment is suppressed.

Abstract: A semiconductor memory device comprises a p.sup.- -type semiconductor substrate (1), p.sup.+ -type regions (15, 80) formed thereon, n.sup.+ -type regions (6, 7) surrounded with the p.sup.+ -type regions (15, 80), a first gate electrode (2) formed on a charge storage region in the n.sup.+ -type region (6), and a second gate electrode (3) formed on the p.sup.+ -type region (80) and serving as a word line. The p.sup.+ -type regions (15, 80) prevent passage of electrons out of electron-hole pairs induced by alpha rays so as to prevent occurrence of soft errors. An oxide film (16) is formed on the side wall of the second gate electrode (3), a titanium silicide film (17) is formed on the n.sup.+ -type regions (6, 7) and a titanium silicide film (18) is formed on the second gate electrode (3) in a self-aligning manner. Therefore, increase of interconnection resistance of the second gate electrode (3 ) and diffusion resistance of the n.sup.+ -type regions (6, 7) is prevented.

Abstract: A semiconductor memory device having memory cells formed adjacent to each other comprises a P type semiconductor substrate having adjacent two trenches, a P.sup.+ impurity region formed in the side portions and the bottom portions of the trenches, n type first polysilicon layers serving as common electrodes formed in the upper portion of the P.sup.+ impurity region through an insulating film, second polysilicon layers formed inside and in the upper portion of the trenches formed of the first polysilicon layers through an insulating film, and a third polysilicon layer formed on the second polysilicon layers, only the third polysilicon layer constituting a connecting electrode between the adjacent memory cells.