Patents by Inventor Katsuhisa Kugimiya

Katsuhisa Kugimiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200057149
    Abstract: The present technology relates to an optical sensor that can suppress a decrease in distance measurement accuracy without increasing power consumption, and an electronic device. The optical sensor includes: a TOF pixel that receives reflected light which is returned when irradiation light emitted from a light emitting unit is reflected on a subject; and a plurality of polarization pixels that respectively receives light beams of a plurality of polarization planes, the light beams being a part of light from the subject. The present technology can be applied to, for example, the cases where distance measurement is performed.
    Type: Application
    Filed: April 27, 2018
    Publication date: February 20, 2020
    Applicant: SONY CORPORATION
    Inventors: Katsuhisa KUGIMIYA, Hiroshi TAKAHASHI, Kenji AZAMI
  • Patent number: 10375282
    Abstract: The present technique relates to a camera module and an electronic apparatus that allow a camera module to be used for various purposes. The camera module includes a first pixel array in which pixels that receive light having an R, G, or B wavelength are two-dimensionally arranged in a matrix form and a second pixel array in which pixels that receive light having a wavelength region of visible light are two-dimensionally arranged in a matrix form and a first optical unit that converges incident light onto the first pixel array and a second optical unit that converges the incident light onto the second pixel array. The present technique can be for example applied to a camera module and the like.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: August 6, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Minoru Ishida, Katsuhisa Kugimiya, Hironori Hoshi
  • Publication number: 20180270404
    Abstract: The present technique relates to a camera module and an electronic apparatus that allow a camera module to be used for various purposes. The camera module includes a first pixel array in which pixels that receive light having an R, G, or B wavelength are two-dimensionally arranged in a matrix form and a second pixel array in which pixels that receive light having a wavelength region of visible light are two-dimensionally arranged in a matrix form and a first optical unit that converges incident light onto the first pixel array and a second optical unit that converges the incident light onto the second pixel array. The present technique can be for example applied to a camera module and the like.
    Type: Application
    Filed: November 10, 2016
    Publication date: September 20, 2018
    Inventors: Minoru ISHIDA, Katsuhisa KUGIMIYA, Hironori HOSHI
  • Patent number: 9917091
    Abstract: A method of manufacturing a semiconductor device, includes: forming an insulating film on a first surface of a semiconductor substrate; and forming a hydrogen supply film on a second surface facing the first surface of the semiconductor substrate, the hydrogen supply film containing one or more of silicon oxide, TEOS, BPSG, BSG, PSG, FSG, carbon-containing silicon oxide, silicon nitride, carbon-containing silicon nitride, and oxygen-containing silicon carbide.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: March 13, 2018
    Assignee: SONY CORPORATION
    Inventors: Katsuhisa Kugimiya, Kenichi Murata, Hitoshi Okano, Shigetaka Mori, Hiroyuki Kawashima, Takuma Matsuno
  • Publication number: 20170207223
    Abstract: A method of manufacturing a semiconductor device, includes: forming an insulating film on a first surface of a semiconductor substrate; and forming a hydrogen supply film on a second surface facing the first surface of the semiconductor substrate, the hydrogen supply film containing one or more of silicon oxide, TEOS, BPSG, BSG, PSG, FSG, carbon-containing silicon oxide, silicon nitride, carbon-containing silicon nitride, and oxygen-containing silicon carbide.
    Type: Application
    Filed: May 28, 2015
    Publication date: July 20, 2017
    Inventors: KATSUHISA KUGIMIYA, KENICHI MURATA, HITOSHI OKANO, SHIGETAKA MORI, HIROYUKI KAWASHIMA, TAKUMA MATSUNO
  • Patent number: 7977140
    Abstract: A method for producing a solid-state imaging device includes steps of: forming transfer electrodes on a substrate having a plurality of light-sensing portions through a gate insulating layer so that the light-sensing portions are exposed; forming a planarized insulating layer on the substrate to cover the transfer electrodes formed on the substrate; forming openings in the planarized insulating layer so that each of the transfer electrodes is partly exposed out of the planarized insulating layer at a predetermined position; forming a wiring material layer so that the openings are filled with the wiring material layer; forming a resist layer on the wiring material layer; exposing and developing the resist layer so that only the resist layer in a predetermined area covering the openings is left; and patterning the wiring material layer using the exposed and developed resist layer to form connection wirings connected to the transfer electrodes by the openings.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: July 12, 2011
    Assignee: Sony Corporation
    Inventors: Takeshi Takeda, Yukihiro Ando, Masaki Okamoto, Masayuki Okada, Kaori Takimoto, Katsuhisa Kugimiya, Tadayuki Kimura
  • Publication number: 20090263929
    Abstract: A method for producing a solid-state imaging device includes steps of: forming transfer electrodes on a substrate having a plurality of light-sensing portions through a gate insulating layer so that the light-sensing portions are exposed; forming a planarized insulating layer on the substrate to cover the transfer electrodes formed on the substrate; forming openings in the planarized insulating layer so that each of the transfer electrodes is partly exposed out of the planarized insulating layer at a predetermined position; forming a wiring material layer so that the openings are filled with the wiring material layer; forming a resist layer on the wiring material layer; exposing and developing the resist layer so that only the resist layer in a predetermined area covering the openings is left; and patterning the wiring material layer using the exposed and developed resist layer to form connection wirings connected to the transfer electrodes by the openings.
    Type: Application
    Filed: March 23, 2009
    Publication date: October 22, 2009
    Applicant: Sony Corporation
    Inventors: Takeshi Takeda, Yukihiro Ando, Masaki Okamoto, Masayuki Okada, Kaori Takimoto, Katsuhisa Kugimiya, Tadayuki Kimura
  • Publication number: 20070298615
    Abstract: A pattern forming method is provided. The pattern forming method includes a first step of forming a resist pattern including a lactone group-containing skeleton above an etched layer provided on a substrate; a second step of performing plasma processing using a hydrogen-containing gas to lower a glass transition temperature or a softening point of the resist pattern; and a third step of transferring the resist pattern after the plasma processing to the etched layer by etching, and forming the pattern of the etched layer.
    Type: Application
    Filed: January 30, 2007
    Publication date: December 27, 2007
    Inventors: Nobuyuki Matsuzawa, Atsuhiro Ando, Eriko Matsui, Yuko Yamaguchi, Katsuhisa Kugimiya, Tetsuya Tatsumi, Salam Kazi, Takeshi Iwai, Makiko Irie
  • Patent number: 6767821
    Abstract: A method of fabricating an interconnect line comprises forming a wall, depositing an etch mask having a thickness that decreases towards a bottom of the wall, and isotropically etching the wall at the bottom to form the interconnect line having a pre-determined gap between the substrate and a bottom of the line.
    Type: Grant
    Filed: April 7, 2003
    Date of Patent: July 27, 2004
    Inventors: Chan-syun David Yang, Ajay Kumar, Wei-Te Wu, Changhun Lee, Yeajer Arthur Chen, Katsuhisa Kugimiya
  • Patent number: 6277763
    Abstract: A method and apparatus for etching of a substrate comprising both a polysilicon layer and an overlying tungsten layer. The method comprises etching the tungsten layer in a chamber using a plasma formed from a gas mixture comprising a fluorinated gas (such as CF4, NF3, SF6, and the like) and oxygen.
    Type: Grant
    Filed: December 16, 1999
    Date of Patent: August 21, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Katsuhisa Kugimiya, Takanori Nishizawa, Daisuke Tajima