Patents by Inventor Katsuhisa Nagao
Katsuhisa Nagao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11908868Abstract: A semiconductor device (1) is manufactured which includes a SiC epitaxial layer (28), a plurality of transistor cells (18) that are formed in the SiC epitaxial layer (28) and that are subjected to ON/OFF control by a predetermined control voltage, a gate electrode (19) that faces a channel region (32) of the transistor cells (18) in which a channel is formed when the semiconductor device (1) is in an ON state, a gate metal (44) that is exposed at the topmost surface for electrical connection with the outside and that is electrically connected to the gate electrode (19) while being physically separated from the gate electrode (19), and a built-in resistor (21) that is made of polysilicon and that is disposed below the gate metal (44) so as to electrically connect the gate metal (44) and the gate electrode (19) together.Type: GrantFiled: May 19, 2022Date of Patent: February 20, 2024Assignee: ROHM CO., LTD.Inventors: Katsuhisa Nagao, Noriaki Kawamoto
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Publication number: 20240014081Abstract: A semiconductor structure for inspection includes a semiconductor plate having a first main surface on one side and a second main surface on the other side, an inspection region provided in the first main surface, a main surface electrode having a first hardness and covering the first main surface in the inspection region, and a protective electrode having a second hardness which exceeds the first hardness, covering the main surface electrode in the inspection region, and forming a current path between the second main surface and the protective electrode via the semiconductor plate.Type: ApplicationFiled: September 26, 2023Publication date: January 11, 2024Applicant: ROHM CO., LTD.Inventors: Toshiro TAKAO, Katsuhisa NAGAO, Yoshiro ENOKIDA
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Patent number: 11862672Abstract: [Object] To provide a semiconductor device capable of improving a discharge starting voltage when measuring electric characteristics, and widening a pad area of a surface electrode or increasing the number of semiconductor devices (number of chips) to be obtained from one wafer, and a method for manufacturing the same. [Solution Means] A semiconductor device 1 includes an n-type SiC layer 2 having a first surface 2A, a second surface 2B, and end faces 2C, a p-type voltage relaxing layer 7 formed in the SiC layer 2 so as to be exposed to the end portion of the first surface 2A of the SiC layer 2, an insulating layer 8 formed on the SiC layer 2 so as to cover the voltage relaxing layer 7, and an anode electrode 9 that is connected to the first surface 2A of the SiC layer 2 through the insulating layer 8 and has a pad area 95 selectively exposed.Type: GrantFiled: June 22, 2021Date of Patent: January 2, 2024Assignee: ROHM CO., LTD.Inventor: Katsuhisa Nagao
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Publication number: 20230273245Abstract: A SiC semiconductor device is provided that is capable of improving the detection accuracy of the current value of a principal current detected by a current sensing portion by restraining heat from escaping from the current sensing portion to a wiring member joined to a sensing-side surface electrode. The semiconductor device 1 includes a SiC semiconductor substrate, a source portion 27 including a principal-current-side unit cell 34, a current sensing portion 26 including a sensing-side unit cell 40, a source-side surface electrode 5 disposed above the source portion 27, and a sensing-side surface electrode 6 that is disposed above the current sensing portion 26 and that has a sensing-side pad 15 to which a sensing-side wire is joined, and, in the semiconductor device 1, the sensing-side unit cell 40 is disposed so as to avoid being positioned directly under the sensing-side pad 15.Type: ApplicationFiled: May 3, 2023Publication date: August 31, 2023Inventor: Katsuhisa NAGAO
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Patent number: 11674983Abstract: A SiC semiconductor device is provided that is capable of improving the detection accuracy of the current value of a principal current detected by a current sensing portion by restraining heat from escaping from the current sensing portion to a wiring member joined to a sensing-side surface electrode. The semiconductor device 1 includes a SiC semiconductor substrate, a source portion 27 including a principal-current-side unit cell 34, a current sensing portion 26 including a sensing-side unit cell 40, a source-side surface electrode 5 disposed above the source portion 27, and a sensing-side surface electrode 6 that is disposed above the current sensing portion 26 and that has a sensing-side pad 15 to which a sensing-side wire is joined, and, in the semiconductor device 1, the sensing-side unit cell 40 is disposed so as to avoid being positioned directly under the sensing-side pad 15.Type: GrantFiled: November 29, 2021Date of Patent: June 13, 2023Assignee: ROHM CO., LTD.Inventor: Katsuhisa Nagao
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Publication number: 20220406887Abstract: [Object] To provide a semiconductor device capable of improving a discharge starting voltage when measuring electric characteristics, and widening a pad area of a surface electrode or increasing the number of semiconductor devices (number of chips) to be obtained from one wafer, and a method for manufacturing the same. [Solution Means] A semiconductor device 1 includes an n-type SiC layer 2 having a first surface 2A, a second surface 2B, and end faces 2C, a p-type voltage relaxing layer 7 formed in the SiC layer 2 so as to be exposed to the end portion of the first surface 2A of the SiC layer 2, an insulating layer 8 formed on the SiC layer 2 so as to cover the voltage relaxing layer 7, and an anode electrode 9 that is connected to the first surface 2A of the SiC layer 2 through the insulating layer 8 and has a pad area 95 selectively exposed.Type: ApplicationFiled: August 5, 2022Publication date: December 22, 2022Inventor: Katsuhisa NAGAO
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Publication number: 20220278133Abstract: A semiconductor device (1) is manufactured which includes a SiC epitaxial layer (28), a plurality of transistor cells (18) that are formed in the SiC epitaxial layer (28) and that are subjected to ON/OFF control by a predetermined control voltage, a gate electrode (19) that faces a channel region (32) of the transistor cells (18) in which a channel is formed when the semiconductor device (1) is in an ON state, a gate metal (44) that is exposed at the topmost surface for electrical connection with the outside and that is electrically connected to the gate electrode (19) while being physically separated from the gate electrode (19), and a built-in resistor (21) that is made of polysilicon and that is disposed below the gate metal (44) so as to electrically connect the gate metal (44) and the gate electrode (19) together.Type: ApplicationFiled: May 19, 2022Publication date: September 1, 2022Inventors: Katsuhisa NAGAO, Noriaki KAWAMOTO
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Publication number: 20220262912Abstract: A semiconductor device includes a semiconductor region made of a material to which conductive impurities are added, an insulating film formed on a surface of the semiconductor region, and an electroconductive gate electrode formed on the insulating film. The gate electrode is made of a material whose Fermi level is closer to a Fermi level of the semiconductor region than a Fermi level of Si in at least a portion contiguous to the insulating film.Type: ApplicationFiled: May 9, 2022Publication date: August 18, 2022Inventors: Yuki NAKANO, Ryota NAKAMURA, Katsuhisa NAGAO
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Patent number: 11367738Abstract: A semiconductor device (1) is manufactured which includes a SiC epitaxial layer (28), a plurality of transistor cells (18) that are formed in the SiC epitaxial layer (28) and that are subjected to ON/OFF control by a predetermined control voltage, a gate electrode (19) that faces a channel region (32) of the transistor cells (18) in which a channel is formed when the semiconductor device (1) is in an ON state, a gate metal (44) that is exposed at the topmost surface for electrical connection with the outside and that is electrically connected to the gate electrode (19) while being physically separated from the gate electrode (19), and a built-in resistor (21) that is made of polysilicon and that is disposed below the gate metal (44) so as to electrically connect the gate metal (44) and the gate electrode (19) together.Type: GrantFiled: December 2, 2020Date of Patent: June 21, 2022Assignee: ROHM CO., LTD.Inventors: Katsuhisa Nagao, Noriaki Kawamoto
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Patent number: 11355609Abstract: A semiconductor device includes a semiconductor region made of a material to which conductive impurities are added, an insulating film formed on a surface of the semiconductor region, and an electroconductive gate electrode formed on the insulating film. The gate electrode is made of a material whose Fermi level is closer to a Fermi level of the semiconductor region than a Fermi level of Si in at least a portion contiguous to the insulating film.Type: GrantFiled: September 10, 2020Date of Patent: June 7, 2022Assignee: ROHM CO., LTD.Inventors: Yuki Nakano, Ryota Nakamura, Katsuhisa Nagao
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Publication number: 20220082593Abstract: A SiC semiconductor device is provided that is capable of improving the detection accuracy of the current value of a principal current detected by a current sensing portion by restraining heat from escaping from the current sensing portion to a wiring member joined to a sensing-side surface electrode. The semiconductor device 1 includes a SiC semiconductor substrate, a source portion 27 including a principal-current-side unit cell 34, a current sensing portion 26 including a sensing-side unit cell 40, a source-side surface electrode 5 disposed above the source portion 27, and a sensing-side surface electrode 6 that is disposed above the current sensing portion 26 and that has a sensing-side pad 15 to which a sensing-side wire is joined, and, in the semiconductor device 1, the sensing-side unit cell 40 is disposed so as to avoid being positioned directly under the sensing-side pad 15.Type: ApplicationFiled: November 29, 2021Publication date: March 17, 2022Inventor: Katsuhisa NAGAO
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Patent number: 11215647Abstract: A SiC semiconductor device is provided that is capable of improving the detection accuracy of the current value of a principal current detected by a current sensing portion by restraining heat from escaping from the current sensing portion to a wiring member joined to a sensing-side surface electrode. The semiconductor device 1 includes a SiC semiconductor substrate, a source portion 27 including a principal-current-side unit cell 34, a current sensing portion 26 including a sensing-side unit cell 40, a source-side surface electrode 5 disposed above the source portion 27, and a sensing-side surface electrode 6 that is disposed above the current sensing portion 26 and that has a sensing-side pad 15 to which a sensing-side wire is joined, and, in the semiconductor device 1, the sensing-side unit cell 40 is disposed so as to avoid being positioned directly under the sensing-side pad 15.Type: GrantFiled: June 3, 2020Date of Patent: January 4, 2022Assignee: ROHM CO., LTD.Inventor: Katsuhisa Nagao
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Publication number: 20210313418Abstract: [Object] To provide a semiconductor device capable of improving a discharge starting voltage when measuring electric characteristics, and widening a pad area of a surface electrode or increasing the number of semiconductor devices (number of chips) to be obtained from one wafer, and a method for manufacturing the same. [Solution Means] A semiconductor device 1 includes an n-type SiC layer 2 having a first surface 2A, a second surface 2B, and end faces 2C, a p-type voltage relaxing layer 7 formed in the SiC layer 2 so as to be exposed to the end portion of the first surface 2A of the SiC layer 2, an insulating layer 8 formed on the SiC layer 2 so as to cover the voltage relaxing layer 7, and an anode electrode 9 that is connected to the first surface 2A of the SiC layer 2 through the insulating layer 8 and has a pad area 95 selectively exposed.Type: ApplicationFiled: June 22, 2021Publication date: October 7, 2021Inventor: Katsuhisa NAGAO
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Patent number: 11075263Abstract: [Object] To provide a semiconductor device capable of improving a discharge starting voltage when measuring electric characteristics, and widening a pad area of a surface electrode or increasing the number of semiconductor devices (number of chips) to be obtained from one wafer, and a method for manufacturing the same. [Solution Means] A semiconductor device 1 includes an n-type SiC layer 2 having a first surface 2A, a second surface 2B, and end faces 2C, a p-type voltage relaxing layer 7 formed in the SiC layer 2 so as to be exposed to the end portion of the first surface 2A of the SiC layer 2, an insulating layer 8 formed on the SiC layer 2 so as to cover the voltage relaxing layer 7, and an anode electrode 9 that is connected to the first surface 2A of the SiC layer 2 through the insulating layer 8 and has a pad area 95 selectively exposed.Type: GrantFiled: January 8, 2019Date of Patent: July 27, 2021Assignee: ROHM CO, , LTD.Inventor: Katsuhisa Nagao
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Publication number: 20210091117Abstract: A semiconductor device (1) is manufactured which includes a SiC epitaxial layer (28), a plurality of transistor cells (18) that are formed in the SiC epitaxial layer (28) and that are subjected to ON/OFF control by a predetermined control voltage, a gate electrode (19) that faces a channel region (32) of the transistor cells (18) in which a channel is formed when the semiconductor device (1) is in an ON state, a gate metal (44) that is exposed at the topmost surface for electrical connection with the outside and that is electrically connected to the gate electrode (19) while being physically separated from the gate electrode (19), and a built-in resistor (21) that is made of polysilicon and that is disposed below the gate metal (44) so as to electrically connect the gate metal (44) and the gate electrode (19) together.Type: ApplicationFiled: December 2, 2020Publication date: March 25, 2021Inventors: Katsuhisa NAGAO, Noriaki KAWAMOTO
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Patent number: 10886300Abstract: A semiconductor device (1) is manufactured which includes a SiC epitaxial layer (28), a plurality of transistor cells (18) that are formed in the SiC epitaxial layer (28) and that are subjected to ON/OFF control by a predetermined control voltage, a gate electrode (19) that faces a channel region (32) of the transistor cells (18) in which a channel is formed when the semiconductor device (1) is in an ON state, a gate metal (44) that is exposed at the topmost surface for electrical connection with the outside and that is electrically connected to the gate electrode (19) while being physically separated from the gate electrode (19), and a built-in resistor (21) that is made of polysilicon and that is disposed below the gate metal (44) so as to electrically connect the gate metal (44) and the gate electrode (19) together.Type: GrantFiled: August 29, 2019Date of Patent: January 5, 2021Assignee: ROHM CO., LTD.Inventors: Katsuhisa Nagao, Noriaki Kawamoto
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Publication number: 20200411655Abstract: A semiconductor device includes a semiconductor region made of a material to which conductive impurities are added, an insulating film formed on a surface of the semiconductor region, and an electroconductive gate electrode formed on the insulating film. The gate electrode is made of a material whose Fermi level is closer to a Fermi level of the semiconductor region than a Fermi level of Si in at least a portion contiguous to the insulating film.Type: ApplicationFiled: September 10, 2020Publication date: December 31, 2020Inventors: Yuki NAKANO, Ryota NAKAMURA, Katsuhisa NAGAO
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Patent number: 10797145Abstract: A semiconductor device includes a semiconductor region made of a material to which conductive impurities are added, an insulating film formed on a surface of the semiconductor region, and an electroconductive gate electrode formed on the insulating film. The gate electrode is made of a material whose Fermi level is closer to a Fermi level of the semiconductor region than a Fermi level of Si in at least a portion contiguous to the insulating film.Type: GrantFiled: October 2, 2019Date of Patent: October 6, 2020Assignee: ROHM CO., LTD.Inventors: Yuki Nakano, Ryota Nakamura, Katsuhisa Nagao
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Publication number: 20200292590Abstract: A SiC semiconductor device is provided that is capable of improving the detection accuracy of the current value of a principal current detected by a current sensing portion by restraining heat from escaping from the current sensing portion to a wiring member joined to a sensing-side surface electrode. The semiconductor device 1 includes a SiC semiconductor substrate, a source portion 27 including a principal-current-side unit cell 34, a current sensing portion 26 including a sensing-side unit cell 40, a source-side surface electrode 5 disposed above the source portion 27, and a sensing-side surface electrode 6 that is disposed above the current sensing portion 26 and that has a sensing-side pad 15 to which a sensing-side wire is joined, and, in the semiconductor device 1, the sensing-side unit cell 40 is disposed so as to avoid being positioned directly under the sensing-side pad 15.Type: ApplicationFiled: June 3, 2020Publication date: September 17, 2020Inventor: Katsuhisa NAGAO
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Publication number: 20200279923Abstract: According to the present invention, a semiconductor device includes a first conductivity type SiC layer, an electrode that is selectively formed upon the SiC layer, and an insulator that is formed upon the SiC layer and that extends to a timing region that is set at an end part of the SiC layer. The insulator includes an electrode lower insulating film that is arranged below the electrode, and an organic insulating layer that is arranged so as to cover the electrode lower insulating film. The length (A) of the interval wherein the organic insulating layer contacts the SiC layer is 40 ?m or more, and the lateral direction distance (B) along the electrode lower insulating layer between the electrode and SiC layer is 40 ?m or more.Type: ApplicationFiled: May 19, 2020Publication date: September 3, 2020Inventors: Katsuhisa NAGAO, Hidetoshi ABE