Abstract: A common mode voltage detection circuit 105 detects a common mode voltage VCM from differential output terminals of a differential output circuit 101. The common mode voltage detection circuit outputs a detected voltage VCM2 in accordance with the common mode voltage VCM. An OTA 106 in the common mode feedback loop inputs or outputs multiple currents of the same phase in accordance with a voltage difference between a reference voltage VCM1 and the detected voltage VCM2. The respective multiple currents of the same phase are inputted/outputted to/from the two respective terminals of the differential output terminals. The common mode voltage can be reduced by flowing the currents into the differential output terminals, and can be increased by leading the currents from the differential output terminals. Thus, a phase margin or a gain margin of a control signal loop can be secured even with low current consumption, thereby realizing stable operation of the circuit.

Abstract: Disclosed is a filter circuit with an order of three or more, comprising at least one means for amplifying an in-band signal, wherein the frequency response of the filter output has a desirable attenuation characteristic obtainable with the order of the filter circuit. The gain of the amplifying means is variably controlled.

Abstract: Disclosed is a reference voltage circuit including control means for performing control so that the voltage of a first current-to-voltage conversion circuit becomes equal to the voltage of a second current-to-voltage conversion circuit; a first current mirror circuit for outputting a current proportionate to the value of a current supplied to the first current-to-voltage conversion circuit or the second current-to-voltage conversion circuit; and a third current-to-voltage conversion circuit for converting the output current from the first current mirror circuit to a voltage, wherein each of the first to third current-to-voltage conversion circuits is configured as follows: a first diode (or a diode-connected first bipolar transistor) is connected in series with a first resistor, and a second resistor is further connected in parallel with the first diode and the first resistor.

Abstract: A correction processing section 1 performs a color correction such that a movement amount indicating how much input values of image signals should be moved for the purpose of color correction becomes smaller as the distance between the input values and the coordinates of the center of region to be corrected becomes larger in the region to be corrected, based on the input values of the input signals (L signal, *a signal, *b signal), conditional data (such as radius r) defining a local region to be corrected, the coordinates (Lc, *ac, *bc) of the center of the region to be corrected and the coordinates (Lm, *am, *bm) of the center of an ideal color region to be targeted.

Abstract: Disclosed is a CMOS current mirror circuit including a first MOS transistor and a second MOS transistor constituting a current mirror, in which a drain of the first MOS transistor and a gate of the second MOS transistor are connected in common, a source of the first MOS transistor is directly grounded, and a gate of the first MOS transistor is connected to the drain of the first MOS transistor through a third MOS transistor which has a source connected to the drain of the first MOS transistor, a drain connected to the gate of the first MOS transistor, and a gate being biased. The source of the second MOS transistor is directly grounded. Current is input to the drain of the third MOS transistor. The drain current of the second MOS transistor is mirrored by cascode current mirror circuits. An output current is output from the source of a MOS transistor for conversion to a voltage by a circuit that receives the current which outputs a reference voltage.

Abstract: A reference voltage circuit includes a first current-voltage converting circuit consisting of a first diode element; a second current-voltage converting circuit consisting of first and second resistances and a second diode element; a third resistance; a first current mirror circuit configured to supply the third resistance with a current which is proportional to a current flowing through the first current-voltage converting circuit or the second current-voltage converting circuit, to generate a reference voltage; and a control section configured to equalize a voltage of the first current-voltage converting circuit and a voltage of the second current-voltage converting circuit. The second diode element and the first resistance are connected in series, and the second resistance is connected in parallel to the series connection of the first resistance and the second diode element.

Abstract: In a quadrature mixer circuit for receiving a radio frequency signal to generate first and second quadrature output signals, a first three-input mixer receives the radio frequency signal, a first local signal having a first frequency and a second local signal having a second frequency to generate the first quadrature output signal, and a second three-input mixer receives the radio frequency signal, the first local signal and the second local signal to generate the second quadrature output signal. The second local signal received by the first three-input mixer and the second local signal received by the second three-input mixer being out of phase by ?/2 from each other.

Abstract: Disclosed is a PLL circuit in which an AC signal with a predetermined frequency is supplied as an input signal to a phase shifter comprising an OTA and a capacitor, and a phase comparator that receives the input signal to the phase shifter and an output signal from the phase shifter outputs a signal corresponding to a phase difference between the input signals. Control is performed so that the phase difference given by the phase shifter becomes a constant value by changing a transconductance (gm) of at the OTA constituting the phase shifter, using an output voltage of an amplifier for amplifying a DC voltage of the output signal of the phase comparator as a control signal.

Abstract: In the DSP which processes an image pickup signal obtained via an optical lens (imaging optical system) and outputs the resulting image pickup signal as processes to an image display section, distortion aberration due to the optical lens is corrected according to a distance from a pixel position corresponding to an optical axis of the optical lens by changing the pixel position for each of a target image in radial directions when the pixel position corresponding to the optical axis is set as a center while suppressing an occurrence of jaggy in the resulting image. With this structure, an image pickup apparatus which corrects distortion aberration by changing pixel position only in radial directions from a pixel position corresponding to an optical axis of the imaging optical system while suppressing an occurrence of jaggy.

Abstract: In a filter apparatus including a master circuit for receiving a reference frequency signal having a reference frequency to generate a control voltage and a slave gm-C filter formed by at least one operational transconductance amplifier and at least one capacitor where the operational transconductance amplifier of the slave gm-C filter is controlled by the control voltage to tune a cut-off frequency or center frequency of the slave gm-C filter, the master circuit is constructed by a phase shifter formed by at least one operational transconductance amplifier and at least one capacitor, the phase shifter being adapted to receive the reference frequency signal and change a phase of the reference frequency signal in accordance with the control voltage, a phase comparator adapted to compare a phase of an output signal of the phase shifter with a phase of the reference frequency signal to generate a phase error signal, and a loop filter adapted to exclude an AC component from the phase error signal to generate a DC

Abstract: In a filter apparatus including a master circuit for receiving a reference frequency signal having a reference frequency to generate a control voltage and a slave gm-C filter formed by at least one operational transconductance amplifier and at least one capacitor where the operational transconductance amplifier of the slave gm-C filter is controlled by the control voltage to tune a cut-off frequency or center frequency of the slave gm-C filter, the master circuit is constructed by first and second gm-C filters each formed by at least one operational transconductance amplifier and at least one capacitor and having different frequency characteristics from each other, the first and second gm-C filters being adapted to receive the reference frequency signal, first and second amplitude detectors having inputs connected to outputs of the first and second gm-C filters, respectively, and a differential amplifier having an input connected to outputs of the first and second amplitude detectors and being adapted to ampl

Abstract: A CMOS reference voltage circuit, preferably formed on a semiconductor integrated circuit, and outputting a reference voltage having a temperature-independent characteristic, comprises first and second diode-connected transistors (or diodes), respectively grounded and driven with two constant currents bearing a constant current ratio to each other, and a unit for amplifying a differential voltage of output voltages from the first and second transistors by a preset factor and for summing the amplified differential voltage to an output voltage of the first or second transistor. The amplifying and summing unit is formed by two OTAs 11, 12 and a current mirror circuit 13.

Abstract: A CMOS reference voltage circuit, preferably formed on a semiconductor integrated circuit, and outputting a reference voltage having a temperature-independent characteristic, comprises first and second diode-connected transistors (or diodes), respectively grounded and driven with two constant currents bearing a constant current ratio to each other, and a unit for amplifying a differential voltage of output voltages from the first and second transistors by a preset factor and for summing the amplified differential voltage to an output voltage of the first or second transistor. The amplifying and summing unit is formed by two OTAs 11, 12 and a current mirror circuit 13.

Abstract: A variable gain amplifier circuit (100) that may have a gain exponentially changed has been disclosed. A variable gain amplifier circuit (100) may include a first OTA (Operational Transconductance Amplifier) (11) and a second OTA (12). A first OTA (11) may receive a differential voltage at input terminals (IN1 and IN2). A second OTA (12) may receive an output from a first OTA (11) and may provide a differential output voltage at output terminals (OUT1 and OUT2). A second OTA (12) may have second OTA input terminals and second OTA output terminals commonly connected to output terminals (OUT1 and OUT2). A small-signal transconductance of the first and second OTAs (11 and 12) may be proportional to driving currents. A first OTA (11) may have a driving current of I0{1+tan h(x/a)} and a second OTA (12) may have a driving current of I0{1?tan h(x/a)}, where ?1<x<1 and a is a constant.

Abstract: A solid-state image sensing apparatus comprises a signal processing section for performing signal processing on an image signal output from a solid-state image sensing device for performing photoelectric conversion of incident light, wherein the signal processing section includes: a temporary storage section for temporarily storing the image signal; and a transmission timing adjusting section for performing the output control of a transmission timing control signal and providing the transmission timing control signal to the temporary storage section such that the image signal stored in the temporary storage section is output within a period other than an image data interval of the image signal output from the solid-state image sensing device.

Abstract: A voltage subtractor/adder circuit has a differential pair having first and second MOS transistors. Gate electrodes of the first and second MOS transistors form input terminals for receiving an input differential voltage. Drain electrodes of the first and second MOS transistors form output terminals for outputting a subtraction output signal. Source electrodes of the first and second MOS transistors are commonly coupled to form an output terminal for addition output voltage. The sum of currents flowing through the first and second MOS transistors increases in proportion to the square of the input differential voltage. It is also possible to drive the differential pair by a constant current source. A level shifter may be provided for level-shifting the addition output voltage from the commonly coupled source electrodes.

Abstract: A data processing apparatus is provided for processing an image signal obtained from a solid-state image pickup device, in which a plurality of types of color filters are discretely provided on pixels, and a pixel to be interpolated and surrounding pixels thereof have image signals. The apparatus comprises an interpolation section for generating a missing color signal in the image signal of each pixel by interpolation using at least the image signals of the surrounding pixels among the image signals of the pixel to be interpolated and the surrounding pixels thereof. The interpolation section obtains an interpolation pattern, which is similar to a pattern of data values of the pixel to be interpolated and the surrounding pixels thereof, depending on uniformity and gradient of the image signals of the pixel to be interpolated and the surrounding pixels thereof, and performs interpolation depending on the interpolation pattern.

Abstract: A common mode voltage detection circuit 105 detects a common mode voltage VCM from differential output terminals of a differential output circuit 101. The common mode voltage detection circuit outputs a detected voltage VCM2 in accordance with the common mode voltage VCM. An OTA 106 in the common mode feedback loop inputs or outputs multiple currents of the same phase in accordance with a voltage difference between a reference voltage VCM1 and the detected voltage VCM2. The respective multiple currents of the same phase are inputted/outputted to/from the two respective terminals of the differential output terminals. The common mode voltage can be reduced by flowing the currents into the differential output terminals, and can be increased by leading the currents from the differential output terminals. Thus, a phase margin or a gain margin of a control signal loop can be secured even with low current consumption, thereby realizing stable operation of the circuit.

Abstract: To provide a linear transconductance amplifier which is easily implemented with LSI and has a linear transconductance superior in a frequency characteristic. In a MOS linear transconductance amplifier according to the present invention, gates of transistors M1 and M2 whose sources are grounded form an input pair, to which a differential voltage is inputted, the gate and drain of a transistor M3 are mutually connected, and drains of the transistors M1, M2 and M3 are mutually connected and are driven by a constant current. The MOS linear transconductance amplifier includes a unit for adding a current flowing in the transistor M1 to a current that is a half of a current flowing in the transistor M3, and a unit for adding a current flowing in the transistor M2, and a current that is a half of a current flowing in the transistor M3, and these two sum currents are made to be differential output current.

Abstract: A MOS differential amplifier circuit has a differential pair having first and second MOS transistors. The source electrodes of the first and second MOS transistors are commonly coupled and driven by a current source, which can be adjusted to change the transconductance of the amplifier. The circuit can be provided with a quadri-tall cell or level shifter in order to provide this operation. With these operational characteristics, the MOS differential pair of this type can be used in a voltage adder/subtractor circuit.