Abstract: In an image sensor according to related art, charge information cannot be read at the same time from a pair of photoelectric conversion elements placed corresponding to one microlens. According to one embodiment, an image sensor includes a first photoelectric conversion element and a second photoelectric conversion element placed corresponding to one microlens, a first transfer transistor placed corresponding to the first photoelectric conversion element and a second transfer transistor placed corresponding to the second photoelectric conversion element, a read timing signal line that supplies a common read timing signal to the first transfer transistor and the second transfer transistor, a first output line that outputs a signal of the first photoelectric conversion element to the outside, and a second output line that outputs a signal of the second photoelectric conversion element to the outside.

Abstract: A solid-state image pickup device includes a column ADC realizing higher precision and higher-speed conversion. Converters converts a signal of each pixels output via a corresponding vertical read line to a digital value by sequentially executing first to N-th (N: integer of three or larger) conversion stages. In the first to (N?1)th conversion stages, each converter determines a value of upper bits including the most significant bit of a digital value by comparing the voltage at a retention stage with a reference voltage while changing the voltage at a retention node. In the N-th conversion stage, each converter determines a value of remaining bits to the least significant bit by comparing the voltage at the retention node with the reference voltage while continuously changing the voltage at the retention node in a range of the voltage step in the (N?1)th conversion stage or a range exceeding the range.

Abstract: In an image sensor according to related art, charge information cannot be read at the same time from a pair of photoelectric conversion elements placed corresponding to one microlens. According to one embodiment, an image sensor includes a first photoelectric conversion element and a second photoelectric conversion element placed corresponding to one microlens, a first transfer transistor placed corresponding to the first photoelectric conversion element and a second transfer transistor placed corresponding to the second photoelectric conversion element, a read timing signal line that supplies a common read timing signal to the first transfer transistor and the second transfer transistor, a first output line that outputs a signal of the first photoelectric conversion element to the outside, and a second output line that outputs a signal of the second photoelectric conversion element to the outside.

Abstract: According to one aspect of the present invention, an image sensor and a sensor module have a configuration in which the image sensor outputs first brightness information representing brightness information of first image information obtained with a first exposure time and second brightness information representing brightness information of second image information obtained with a second exposure time separately from a composite image obtained by synthesizing the first image information and the second image information, updates the first and second exposure times based on an exposure time set value externally generated based on the first brightness information and the second brightness information, and changes a synthesis set value used for synthesis of the composite image based on the exposure time set value externally generated based on the first brightness information and the second brightness information.

Abstract: In an image sensor according to related art, charge information cannot be read at the same time from a pair of photoelectric conversion elements placed corresponding to one microlens. According to one embodiment, an image sensor includes a first photoelectric conversion element and a second photoelectric conversion element placed corresponding to one microlens, a first transfer transistor placed corresponding to the first photoelectric conversion element and a second transfer transistor placed corresponding to the second photoelectric conversion element, a read timing signal line that supplies a common read timing signal to the first transfer transistor and the second transfer transistor, a first output line that outputs a signal of the first photoelectric conversion element to the outside, and a second output line that outputs a signal of the second photoelectric conversion element to the outside.

Abstract: An image pickup apparatus that makes it possible to achieve both high picture quality and a wide dynamic range is provided. Each pixel unit included in the image pickup apparatus includes: four photodiodes; four transfer transistors; a charge storage portion (four floating diffusions) for storing electric charges generated at the photodiodes; an amplification transistor; a select transistor; and a reset transistor. The image pickup apparatus further includes multiple coupling transistors. Each coupling transistor couples together the charge storage portions of two pixel units of the pixel units. A scanning circuit switches on or off the coupling transistors according to read mode.

Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

Abstract: An image pickup apparatus that makes it possible to achieve both high picture quality and a wide dynamic range is provided. Each pixel unit included in the image pickup apparatus includes: four photodiodes; four transfer transistors; a charge storage portion (four floating diffusions) for storing electric charges generated at the photodiodes; an amplification transistor; a select transistor; and a reset transistor. The image pickup apparatus further includes multiple coupling transistors. Each coupling transistor couples together the charge storage portions of two pixel units of the pixel units. A scanning circuit switches on or off the coupling transistors according to read mode.

Abstract: There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.

Abstract: According to one aspect of the present invention, an image sensor and a sensor module have a configuration in which the image sensor outputs first brightness information representing brightness information of first image information obtained with a first exposure time and second brightness information representing brightness information of second image information obtained with a second exposure time separately from a composite image obtained by synthesizing the first image information and the second image information, updates the first and second exposure times based on an exposure time set value externally generated based on the first brightness information and the second brightness information, and changes a synthesis set value used for synthesis of the composite image based on the exposure time set value externally generated based on the first brightness information and the second brightness information.

Abstract: In an image sensor according to related art, charge information cannot be read at the same time from a pair of photoelectric conversion elements placed corresponding to one microlens. According to one embodiment, an image sensor includes a first photoelectric conversion element and a second photoelectric conversion element placed corresponding to one microlens, a first transfer transistor placed corresponding to the first photoelectric conversion element and a second transfer transistor placed corresponding to the second photoelectric conversion element, a read timing signal line that supplies a common read timing signal to the first transfer transistor and the second transfer transistor, a first output line that outputs a signal of the first photoelectric conversion element to the outside, and a second output line that outputs a signal of the second photoelectric conversion element to the outside.

Abstract: There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.

Abstract: There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.

Abstract: A solid-state image pickup device includes a column ADC realizing higher precision and higher-speed conversion. Converters converts a signal of each pixels output via a corresponding vertical read line to a digital value by sequentially executing first to N-th (N: integer of three or larger) conversion stages. In the first to (N?1)th conversion stages, each converter determines a value of upper bits including the most significant bit of a digital value by comparing the voltage at a retention stage with a reference voltage while changing the voltage at a retention node. In the N-th conversion stage, each converter determines a value of remaining bits to the least significant bit by comparing the voltage at the retention node with the reference voltage while continuously changing the voltage at the retention node in a range of the voltage step in the (N?1)th conversion stage or a range exceeding the range.

Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

Abstract: A solid-state image pickup device includes a column ADC realizing higher precision and higher-speed conversion. Converters converts a signal of each pixels output via a corresponding vertical read line to a digital value by sequentially executing first to N-th (N: integer of three or larger) conversion stages. In the first to (N?1)th conversion stages, each converter determines a value of upper bits including the most significant bit of a digital value by comparing the voltage at a retention stage with a reference voltage while changing the voltage at a retention node. In the N-th conversion stage, each converter determines a value of remaining bits to the least significant bit by comparing the voltage at the retention node with the reference voltage while continuously changing the voltage at the retention node in a range of the voltage step in the (N?1)th conversion stage or a range exceeding the range.

Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

Abstract: An image pickup apparatus that makes it possible to achieve both high picture quality and a wide dynamic range is provided. Each pixel unit included in the image pickup apparatus includes: four photodiodes; four transfer transistors; a charge storage portion (four floating diffusions) for storing electric charges generated at the photodiodes; an amplification transistor; a select transistor; and a reset transistor. The image pickup apparatus further includes multiple coupling transistors. Each coupling transistor couples together the charge storage portions of two pixel units of the pixel units. A scanning circuit switches on or off the coupling transistors according to read mode.

Abstract: An image pickup apparatus that makes it possible to achieve both high picture quality and a wide dynamic range is provided. Each pixel unit included in the image pickup apparatus includes: four photodiodes; four transfer transistors; a charge storage portion (four floating diffusions) for storing electric charges generated at the photodiodes; an amplification transistor; a select transistor; and a reset transistor. The image pickup apparatus further includes multiple coupling transistors. Each coupling transistor couples together the charge storage portions of two pixel units of the pixel units. A scanning circuit switches on or off the coupling transistors according to read mode.

Abstract: There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.