Patents by Inventor Katsumi Hoashi

Katsumi Hoashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080192146
    Abstract: In the case of performing NR (noise reduction) and scaling on video signals, the NR buffer 104 is formed by, for example, five line memories. An NR section 103 and a scaling section 105 are controlled by a control section 108. The control section 108 controls the NR section 103 and the scaling section 105 such that video signals subjected to noise reduction by the NR section 103 and corresponding to one line are output from the NR section 103 to an arbitrary one of the line memories of the NR buffer 104 and video signals corresponding to a plurality of lines and stored in the line memories of the NR buffer 104 except for the line memory to which the video signals corresponding to one line have been input from the NR section 103 are input from the NR buffer 104 to the scaling section 105. Accordingly, noise components of video signals are reduced with the memory size reduced.
    Type: Application
    Filed: September 1, 2005
    Publication date: August 14, 2008
    Inventors: Akifumi Yamana, Katsumi Hoashi
  • Patent number: 7386180
    Abstract: An image signal reproduction apparatus and an image signal reproduction method that can reproduce video signals at high speed with stability. A skip decoding field counter is set on the basis of a factor by which the reproduction speed is multiplied and the number of fields included in one frame image. When decoding of coded data corresponding to one frame to be decoded is completed, it is judged whether the skip decoding field counter is larger than zero or not. When the counter is larger than zero, the number of fields corresponding to a picture to be skipped is subtracted from the counter, and when the picture to be skipped is I or P coded data, the decoding is instructed, while when the picture is B coded data, the skipping is instructed. These processes are repeated until the counter becomes 0 or smaller.
    Type: Grant
    Filed: February 4, 2004
    Date of Patent: June 10, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akira Sota, Katsumi Hoashi, Ryoji Yamaguchi
  • Publication number: 20080030619
    Abstract: The present invention provides a digital image receiving device and a digital image receiving method, wherein VBI (Vertical Blanking Interval) data can also be used as valid data. The digital image receiving device includes: an image capturing section for capturing digital image data, including image data and VBI data, and outputting the captured data; a storage section for storing the captured data; an image output section for reading out data stored in the storage section and outputting the read-out data; and a control section for controlling the image capturing section so that when the capturing process is performed, not only the image data but also the VBI data are captured and output to, and stored in, the storage section.
    Type: Application
    Filed: May 26, 2005
    Publication date: February 7, 2008
    Inventors: Katsumi Hoashi, Ryoji Yamaguchi
  • Publication number: 20080025410
    Abstract: A decode control section 103 sets allocated times required for decoding a plurality of coded streams in processing units based on input stream information on the plurality of coded streams. A decode section 101 decodes the plurality of coded streams while switching the input between the plurality of coded streams based on the allocated times.
    Type: Application
    Filed: December 20, 2005
    Publication date: January 31, 2008
    Inventors: Tomoko Matsui, Ryoji Yamaguchi, Katsumi Hoashi
  • Publication number: 20070206870
    Abstract: There are included an image decoder (10) for decoding encoded image data; a processor (11) for performing both a partial decoding of encoded image data and a control of the image decoder (10); an internal command memory (12) for storing programs to be executed by the processor (11); an external command memory (13) for storing all of programs to be transferred to a RAM area of the processor (11); and a frame memory (14) for storing decoded data outputted from the image decoder (10). The programs used for decoding the encoded image data are divided into functional module units. While the programs are interchanged from the external command memory (13) to the internal command memory (12) for each of predetermined command memory transfer unit during reproduction, the encoded image data is decoded.
    Type: Application
    Filed: December 8, 2004
    Publication date: September 6, 2007
    Inventors: Katsumi Hoashi, Ryoji Yamaguchi
  • Publication number: 20040179611
    Abstract: An image signal reproduction apparatus and an image signal reproduction method that can reproduce video signals at high speed with stability. A skip decoding field counter is set on the basis of a factor by which the reproduction speed is multiplied and the number of fields included in one frame image. When decoding of coded data corresponding to one frame to be decoded is completed, it is judged whether the skip decoding field counter is larger than zero or not. When the counter is larger than zero, the number of fields corresponding to a picture to be skipped is subtracted from the counter, and when the picture to be skipped is I or P coded data, the decoding is instructed, while when the picture is B coded data, the skipping is instructed. These processes are repeated until the counter becomes 0 or smaller.
    Type: Application
    Filed: February 4, 2004
    Publication date: September 16, 2004
    Inventors: Akira Sota, Katsumi Hoashi, Ryoji Yamaguchi
  • Patent number: 6567131
    Abstract: Decoded data, which has been output from a decoder, is stored on storage so as to be presented or used for decoding another encoded data. A presentation method recognizer recognizes a presentation method for the decoded data. If the presentation method has been changed into a new presentation method, the recognizer sets the number of frame memories as required by the new presentation method. In that case, a memory allocator allocates the same number of sub-areas of the storage area as that set by the recognizer for the frame memories such that the sub-area previously allocated for the frame memory, on which the decoded data being presented is stored, is included in the sub-areas newly allocated.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: May 20, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Katsumi Hoashi