Abstract: In a POS terminal device (1) according to the present invention, a rotation center of an operator-side rotation shaft (31) is at a position spaced apart from a longitudinal center line of a housing (2), a rotation center of a customer-side rotation shaft (41) is at a position spaced apart from the center line on an opposite side of the operator-side rotation shaft (31), an operator display (3) is rotated by 90 degrees in a horizontal direction around the operator-side rotation shaft (31) in such a way that a lateral end surface having a shorter distance from the rotation center of the operator-side rotation shaft (31) approaches a customer display (4), and the customer display (4) is rotated by 90 degrees in the horizontal direction around the customer-side rotation shaft (41) in the same direction as the operator display (3).

Abstract: There is provided an electric telescopic stick of which length can be easily adjusted quickly if needed by using only one hand by providing a multiple thread screw and providing a switch on an anterior portion of a grip portion including an electric motor which rotates the multiple thread screw in the forward and reverse directions. Further, in the electric telescopic stick, since a clutch is formed between the electric motor and the multiple thread screw, overload is not applied to the motor because the clutch idles when the movable stick portion is completely elongated. Further, a user can recognize the idling state from hitting sounds generated when steel balls are hit against holes when the clutch idles.

Abstract: To obtain a correct vector address even if an interrupt occurs during erasing or programming of the data in a built-in ROM 18 by moving a part of a built-in RAM13 to a vector address area by a bus controller 27. Thereby, a microcomputer is prevented from running away and the safety of a system is improved at the time of on-board programming of the built-in ROM 18.

Abstract: To obtain a correct vector address even if an interrupt occurs during erasing or programming of the data in a built-in ROM 18 by moving a part of a built-in RAM 13 to a vector address area by a bus controller 27. Thereby, a microcomputer is prevented from running away and the safety of a system is improved at the time of on-board programming of the built-in ROM 18.

Abstract: A data processor includes the normal mode providing narrow access space of CPU and the advance mode providing wide access space. Even in the normal mode, the transfer control section assures data transfer control exceeding the address range for access from CPU. Even when programs are generated exceeding the limit of program capacity for the access range of CPU in the normal mode, if the programs exceeding such limit are stored in the non-access area of ROM 6 in the normal mode, the transfer control section accesses such programs and transfers these programs to RAM. Thereby CPU in the normal mode can use such programs transferred to RAM by making access thereto. Accordingly, limit of program capacity can be alleviated, while maintaining good program execution efficiency in the rather small access space of CPU in the data processor.

Abstract: To obtain a correct vector address even if an interrupt occurs during erasing or programming of the data in a built-in ROM 18 by moving a part of a built-in RAM 13 to a vector address area by a bus controller 27. Thereby, a microcomputer is prevented from running away and the safety of a system is improved at the time of on-board programming of the built-in ROM 18.

Abstract: An interface controller is designed to separately define the first control information to be supplied to the first latch means for controlling an operation of an interface-controlled device connected to the same controller and the second control information to be supplied to the second latch means for controlling an interface operation with the interface-controlled device, in a form of a pair of the first and second information. When there is an addition or a change in a command defined for the interface-controlled device, as for a command transmission to the interface-controlled device and as for an interface control operation of the interface controller itself, both the control information can be independently amended to cope with the addition or the change.

Abstract: To obtain a correct vector address even if an interrupt occurs during erasing or programming of the data in a built-in ROM 18 by moving a part of a built-in RAM13 to a vector address area by a bus controller 27. Thereby, a microcomputer is prevented from running away and the safety of a system is improved at the time of on-board programming of the built-in ROM 18.

Abstract: To obtain a correct vector address even if an interrupt occurs during erasing or programing of the data in a built-in ROM 18 by moving a part of a built-in RAM13 to a vector address area by a bus controller 27. Thereby, a microcomputer is prevented from running away and the safety of a system is improved at the time of on-board programming of the built-in ROM 18.

Abstract: To obtain a correct vector address even if an interrupt occurs during erasing or programming of the data in a built-in ROM 18 by moving a part of a built-in RAM13 to a vector address area by a bus controller 27. Thereby, a microcomputer is prevented from running away and the safety of a system is improved at the time of on-board programming of the built-in ROM 18.

Abstract: A microcomputer constructed on a single semiconductor substrate comprises a microprocessor CPU, a read only memory ROM, a random access memory RAM, a common bus BUS for electrically connecting the microprocessor CPU, the read only memory ROM and the random access memory RAM, a plurality of timers TM, a plurality of input/output circuits I/O, a network portion NET for bringing the timers TM and the input/output circuits I/O into a desired connectional form, and a control register CRG for controlling the network portion NET.The control register CRG is coupled to the common bus BUS, and can have control bit information written thereinto by the microprocessor CPU. On the basis of the control bit information stored in the control register CRG, the network portion NET connects the timers TM and/or the input/output circuits I/O so as to achieve a specified circuit arrangement instructed by the control bit information.

Abstract: Operation of a clock generating circuit is stopped when the oscillation signals to be selectively transmitted to the clock generating circuit via a multiplexer are switched. The oscillation signals are generated by a first oscillation circuit at a relatively high frequency and by a second oscillation circuit which steadily oscillates at a relatively low frequency. The clock generating operation is resumed in synchronization with the switched oscillation signals.

Abstract: An automatic coating system for making set-up by coating a wax pattern with a refractory material, for use in a lost wax process. The system has a set-up pickup device adapted to pickup the set-ups by one from a set-up pool, a slurry dipping device for dipping the set-up in the slurry of the refractory coating material, a sanding device adapted to deposit sand to the coated set-up and a set-up taking-out device for taking the set-up out of the system. These devices are disposed on a common circle. The system further has aset-up transportation device located at the center of the circle. The transportation device has a plurality of beams extended radially outwardly to positions of the devices on the circle and supported by a shaft which is rotatable and movable up and down. Each beam has an arm which is adapted to hold the set-up. The beams of the transportation device are cyclically moved up and down and rotated back and forth to transport the set-ups from one to the next devices disposed on the circle.