Patents by Inventor Katsumi Koge
Katsumi Koge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240244836Abstract: A semiconductor device includes: a substrate; a memory cell region over the substrate; a peripheral region over the substrate, the peripheral region being adjacent to the memory cell region; and a plurality of first and second word-lines extending across the memory cell region and the peripheral region; wherein the plurality of first word-lines and the plurality of second word-lines are arranged alternately with each other; and wherein the length of the first word-line in the peripheral region is longer than the length of the second word-line in the peripheral region.Type: ApplicationFiled: March 29, 2024Publication date: July 18, 2024Applicant: MICRON TECHNOLOGY, INC.Inventors: Hidenori Yamaguchi, Katsumi Koge, Junya Suzuki, Hiroshi Ichikawa
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Patent number: 11581278Abstract: A semiconductor device includes a first layer including a plurality of wirings arranged in line and space layout and a second layer including a pad electrically connected to at least one of the wirings, wherein the wirings and the pads are patterned by different lithographic processes.Type: GrantFiled: October 19, 2020Date of Patent: February 14, 2023Assignee: Micron Technology, Inc.Inventors: Hidenori Yamaguchi, Shunsuke Asanao, Katsumi Koge, Shigeharu Nishimura
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Publication number: 20220406792Abstract: A semiconductor device includes: a substrate; a memory cell region over the substrate; a peripheral region over the substrate, the peripheral region being adjacent to the memory cell region; and a plurality of first and second word-lines extending across the memory cell region and the peripheral region; wherein the plurality of first word-lines and the plurality of second word-lines are arranged alternately with each other; and wherein the length of the first word-line in the peripheral region is longer than the length of the second word-line in the peripheral region.Type: ApplicationFiled: June 22, 2021Publication date: December 22, 2022Applicant: MICRON TECHNOLOGY, INC.Inventors: Hidenori Yamaguchi, Katsumi Koge, Junya Suzuki, Hiroshi Ichikawa
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Patent number: 11393828Abstract: A semiconductor device comprises laterally-neighboring word lines having respective word line caps thereon, an active region between the laterally-neighboring word lines and word line caps, an insulating material and a semiconductive material adjacent the word line caps, and a digit line contact between opposing substantially vertical surfaces of the semiconductive material, between opposing substantially vertical surfaces of the insulating material, adjacent to substantially horizontal surfaces of the word line caps, and between opposing substantially vertical surfaces of the word line caps. A transition surface extending between and connecting the substantially horizontal surface and the substantially vertical surface of the respective word line caps projects toward a longitudinal axis extending centrally through the digit line contact. Methods of forming the semiconductor device are also disclosed, as are electronic systems including the semiconductor device.Type: GrantFiled: August 27, 2020Date of Patent: July 19, 2022Assignee: Micron Technology, Inc.Inventors: Naoyoshi Kobayashi, Osamu Fujita, Katsumi Koge
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Publication number: 20220122931Abstract: A semiconductor device includes a first layer including a plurality of wirings arranged in line and space layout and a second layer including a pad electrically connected to at least one of the wirings, wherein the wirings and the pads are patterned by different lithographic processes.Type: ApplicationFiled: October 19, 2020Publication date: April 21, 2022Applicant: MICRON TECHNOLOGY, INC.Inventors: Hidenori Yamaguchi, Shunsuke Asanao, Katsumi Koge, Shigeharu Nishimura
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Patent number: 11239240Abstract: A semiconductor device comprises semiconductive pillars; digit lines laterally between the semiconductive pillars; nitride caps vertically overlying the digit lines; nitride structures overlying surfaces of the nitride caps; redistribution material structures comprising upper portions overlying upper surfaces of the nitride caps and the nitride structures, and lower portions overlying upper surfaces of the semiconductive pillars; a low-K dielectric material laterally between the digit lines and the semiconductive pillars; air gaps laterally between the low-K dielectric material and the semiconductive pillars, and having upper boundaries below the upper surfaces of the nitride caps; and a nitride dielectric material laterally between the air gaps and the semiconductive pillars. Memory devices, electronic systems, and method of forming a semiconductor device are also described.Type: GrantFiled: June 16, 2020Date of Patent: February 1, 2022Assignee: Micron Technology, Inc.Inventors: Arzum F. Simsek-Ege, Guangjun Yang, Kuo-Chen Wang, Mohd Kamran Akhtar, Katsumi Koge
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Publication number: 20200395365Abstract: A semiconductor device comprises laterally-neighboring word lines having respective word line caps thereon, an active region between the laterally-neighboring word lines and word line caps, an insulating material and a semiconductive material adjacent the word line caps, and a digit line contact between opposing substantially vertical surfaces of the semiconductive material, between opposing substantially vertical surfaces of the insulating material, adjacent to substantially horizontal surfaces of the word line caps, and between opposing substantially vertical surfaces of the word line caps. A transition surface extending between and connecting the substantially horizontal surface and the substantially vertical surface of the respective word line caps projects toward a longitudinal axis extending centrally through the digit line contact. Methods of forming the semiconductor device are also disclosed, as are electronic systems including the semiconductor device.Type: ApplicationFiled: August 27, 2020Publication date: December 17, 2020Inventors: Naoyoshi Kobayashi, Osamu Fujita, Katsumi Koge
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Publication number: 20200312857Abstract: A semiconductor device comprises semiconductive pillars; digit lines laterally between the semiconductive pillars; nitride caps vertically overlying the digit lines; nitride structures overlying surfaces of the nitride caps; redistribution material structures comprising upper portions overlying upper surfaces of the nitride caps and the nitride structures, and lower portions overlying upper surfaces of the semiconductive pillars; a low-K dielectric material laterally between the digit lines and the semiconductive pillars; air gaps laterally between the low-K dielectric material and the semiconductive pillars, and having upper boundaries below the upper surfaces of the nitride caps; and a nitride dielectric material laterally between the air gaps and the semiconductive pillars. Memory devices, electronic systems, and method of forming a semiconductor device are also described.Type: ApplicationFiled: June 16, 2020Publication date: October 1, 2020Inventors: Arzum F. Simsek-Ege, Guangjun Yang, Kuo-Chen Wang, Mohd Kamran Akhtar, Katsumi Koge
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Patent number: 10770466Abstract: A semiconductor device comprises laterally-neighboring word lines having respective word line caps thereon, an active region between the laterally-neighboring word lines and word line caps, an insulating material and a semiconductive material adjacent the word line caps, and a digit line contact between opposing substantially vertical surfaces of the semiconductive material, between opposing substantially vertical surfaces of the insulating material, adjacent to substantially horizontal surfaces of the word line caps, and between opposing substantially vertical surfaces of the word line caps. A transition surface extending between and connecting the substantially horizontal surface and the substantially vertical surface of the respective word line caps projects toward a longitudinal axis extending centrally through the digit line contact. Methods of forming the semiconductor device are also disclosed, as are electronic systems including the semiconductor device.Type: GrantFiled: January 25, 2019Date of Patent: September 8, 2020Assignee: Micron Technology, Inc.Inventors: Naoyoshi Kobayashi, Osamu Fujita, Katsumi Koge
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Publication number: 20200243539Abstract: A semiconductor device comprises laterally-neighboring word lines having respective word line caps thereon, an active region between the laterally-neighboring word lines and word line caps, an insulating material and a semiconductive material adjacent the word line caps, and a digit line contact between opposing substantially vertical surfaces of the semiconductive material, between opposing substantially vertical surfaces of the insulating material, adjacent to substantially horizontal surfaces of the word line caps, and between opposing substantially vertical surfaces of the word line caps. A transition surface extending between and connecting the substantially horizontal surface and the substantially vertical surface of the respective word line caps projects toward a longitudinal axis extending centrally through the digit line contact. Methods of forming the semiconductor device are also disclosed, as are electronic systems including the semiconductor device.Type: ApplicationFiled: January 25, 2019Publication date: July 30, 2020Inventors: Naoyoshi Kobayashi, Osamu Fujita, Katsumi Koge
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Patent number: 10707215Abstract: A semiconductor device comprises semiconductive pillars; digit lines laterally between the semiconductive pillars; nitride caps vertically overlying the digit lines; nitride structures overlying surfaces of the nitride caps; redistribution material structures comprising upper portions overlying upper surfaces of the nitride caps and the nitride structures, and lower portions overlying upper surfaces of the semiconductive pillars; a low-K dielectric material laterally between the digit lines and the semiconductive pillars; air gaps laterally between the low-K dielectric material and the semiconductive pillars, and having upper boundaries below the upper surfaces of the nitride caps; and a nitride dielectric material laterally between the air gaps and the semiconductive pillars. Memory devices, electronic systems, and method of forming a semiconductor device are also described.Type: GrantFiled: August 22, 2018Date of Patent: July 7, 2020Assignee: Micron Technology, Inc.Inventors: Arzum F. Simsek-Ege, Guangjun Yang, Kuo-Chen Wang, Mohd Kamran Akhtar, Katsumi Koge
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Publication number: 20200066729Abstract: A semiconductor device comprises semiconductive pillars; digit lines laterally between the semiconductive pillars; nitride caps vertically overlying the digit lines; nitride structures overlying surfaces of the nitride caps; redistribution material structures comprising upper portions overlying upper surfaces of the nitride caps and the nitride structures, and lower portions overlying upper surfaces of the semiconductive pillars; a low-K dielectric material laterally between the digit lines and the semiconductive pillars; air gaps laterally between the low-K dielectric material and the semiconductive pillars, and having upper boundaries below the upper surfaces of the nitride caps; and a nitride dielectric material laterally between the air gaps and the semiconductive pillars. Memory devices, electronic systems, and method of forming a semiconductor device are also described.Type: ApplicationFiled: August 22, 2018Publication date: February 27, 2020Inventors: Arzum F. Simsek-Ege, Guangjun Yang, Kuo-Chen Wang, Mohd Kamran Akhtar, Katsumi Koge
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Patent number: 10128183Abstract: A method of forming a conductive via comprises forming a structure comprising an elevationally-extending-conductive via and a conductive line electrically coupled to and crossing above the conductive via. The conductive line comprises first conductive material and the conductive via comprises second conductive material of different composition from that of the first conductive material. The conductive line and the conductive via respectively having opposing sides in a vertical cross-section. First insulator material having k no greater than 4.0 is formed laterally outward of the opposing sides of the second conductive material of the conductive via selectively relative to the first conductive material of the opposing sides of the conductive line. The first insulator material is formed to a lateral thickness of at least 40 Angstroms in the vertical cross-section. Second insulator material having k greater than 4.Type: GrantFiled: March 20, 2018Date of Patent: November 13, 2018Assignee: Micron Technology, Inc.Inventors: Sourabh Dhir, Andrew L. Li, Sanh D. Tang, Naoyoshi Kobayashi, Katsumi Koge
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Publication number: 20180323142Abstract: A method of forming a conductive via comprises forming a structure comprising an elevationally-extending-conductive via and a conductive line electrically coupled to and crossing above the conductive via. The conductive line comprises first conductive material and the conductive via comprises second conductive material of different composition from that of the first conductive material. The conductive line and the conductive via respectively having opposing sides in a vertical cross-section. First insulator material having k no greater than 4.0 is formed laterally outward of the opposing sides of the second conductive material of the conductive via selectively relative to the first conductive material of the opposing sides of the conductive line. The first insulator material is formed to a lateral thickness of at least 40 Angstroms in the vertical cross-section. Second insulator material having k greater than 4.Type: ApplicationFiled: March 20, 2018Publication date: November 8, 2018Applicant: Micron Technology, Inc.Inventors: Sourabh Dhir, Andrew L. Li, Sanh D. Tang, Naoyoshi Kobayashi, Katsumi Koge
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Patent number: 9960114Abstract: A method of forming a conductive via comprises forming a structure comprising an elevationally-extending-conductive via and a conductive line electrically coupled to and crossing above the conductive via. The conductive line comprises first conductive material and the conductive via comprises second conductive material of different composition from that of the first conductive material. The conductive line and the conductive via respectively having opposing sides in a vertical cross-section. First insulator material having k no greater than 4.0 is formed laterally outward of the opposing sides of the second conductive material of the conductive via selectively relative to the first conductive material of the opposing sides of the conductive line. The first insulator material is formed to a lateral thickness of at least 40 Angstroms in the vertical cross-section. Second insulator material having k greater than 4.Type: GrantFiled: May 3, 2017Date of Patent: May 1, 2018Assignee: Micron Technology, Inc.Inventors: Sourabh Dhir, Andrew L. Li, Sanh D. Tang, Naoyoshi Kobayashi, Katsumi Koge
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Publication number: 20160027783Abstract: One production method for semiconductor devices includes sequentially forming a stopper film and a BPSG film, forming a cylinder etch laminated mask upon the BPSG film, forming openings having a prescribed pattern in the cylinder etch laminated mask, then, using same as a mask, forming a cylinder hole that pierces from the BPSG film to the stopper film in the thickness direction. Next, forming a conductive layer that adjoins the side surfaces of the BPSG film, the stopper film, and a polysilicon film being part of the cylinder etch laminated mask, then removing the polysilicon film and the BPSG film .Type: ApplicationFiled: March 10, 2014Publication date: January 28, 2016Inventor: Katsumi Koge
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Patent number: 8043903Abstract: A method of manufacturing a semiconductor device may include, but is not limited to the following processes. A first recess is formed in a semiconductor substrate to define an active region on the semiconductor substrate. The active region includes a protruding portion of the semiconductor substrate surrounded by the first recess. The protruding portion has a sloped side surface. A first insulating film that fills the first recess is formed. A gate recess is formed in the active region to form a thin film portion that upwardly extends. The thin film portion is positioned between the gate recess and the first insulating film. The thin film portion is a part of the protruding portion. An upper part of the thin film portion is removed by wet-etching to adjust a height of the thin film portion.Type: GrantFiled: October 1, 2010Date of Patent: October 25, 2011Assignee: Elpida Memory, Inc.Inventors: Katsumi Koge, Teruyuki Mine, Yasushi Yamazaki
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Publication number: 20110081761Abstract: A method of manufacturing a semiconductor device may include, but is not limited to the following processes. A first recess is formed in a semiconductor substrate to define an active region on the semiconductor substrate. The active region includes a protruding portion of the semiconductor substrate surrounded by the first recess. The protruding portion has a sloped side surface. A first insulating film that fills the first recess is formed. A gate recess is formed in the active region to form a thin film portion that upwardly extends. The thin film portion is positioned between the gate recess and the first insulating film. The thin film portion is a part of the protruding portion. An upper part of the thin film portion is removed by wet-etching to adjust a height of the thin film portion.Type: ApplicationFiled: October 1, 2010Publication date: April 7, 2011Applicant: ELPIDA MEMORY, INC.Inventors: KATSUMI KOGE, TERUYUKI MINE, YASUSHI YAMAZAKI