Patents by Inventor Katsumi Nakamura

Katsumi Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250133361
    Abstract: A method of processing sound includes arranging objects of a plurality of performers in a virtual space. The method also includes receiving a plurality of sound signals respectively corresponding to the plurality of performers. The method also includes obtaining, using a trained model, sound volume adjustment parameters respectively for the plurality of performers. The trained model is trained to learn a relationship between each sound signal, among the plurality of sound signals, that corresponds to each performer of the plurality of performers and each sound volume adjustment parameter, among the sound volume adjustment parameters, that corresponds to the each sound signal. The method also includes adjusting and mixing sound volumes respectively of the plurality of sound signals based on the sound volume adjustment parameters obtained using the trained model.
    Type: Application
    Filed: December 24, 2024
    Publication date: April 24, 2025
    Inventors: Futoshi SHIRAKIHARA, Ryo MATSUDA, Yoshinari NAKAMURA, Yuya TAKENAKA, Katsumi ISHIKAWA, Akio OHTANI, Kazuhiko YAMAMOTO, Takuya FUJISHIMA
  • Patent number: 12278280
    Abstract: A semiconductor device includes: an N? drift layer of a first conductivity type formed in the semiconductor substrate; a P base layer formed on the N? drift layer; and an N buffer layer of the first conductivity type formed under the N? drift layer and higher in peak impurity concentration than the N? drift layer. The N buffer layer includes: a first buffer layer in which a trap level derived from lattice defect is not detected by a photoluminescence method; and a second buffer layer provided between the first buffer layer and the N? drift layer and in which two types of trap levels derived from lattice defect are detected by the photoluminescence method.
    Type: Grant
    Filed: February 5, 2024
    Date of Patent: April 15, 2025
    Assignee: Mitsubishi Electric Corporation
    Inventor: Katsumi Nakamura
  • Publication number: 20250110629
    Abstract: The operation terminal device includes a control unit, and a user interface unit including a touch panel and controlled by the control unit. The control unit has a display control function of displaying a setting screen of a plurality of setting screens on the touch panel and controlling the display such that the setting screen is switched to another setting screen in response to an operation of the user on the touch panel. The display control function includes a function of controlling such that, in a case where the setting screen is switched to the other setting screen, a selection element that is currently set among a plurality of selection elements provided on the other setting screen and selectable by the user is displayed for a predetermined time, and the other selection element is displayed in a selectable manner together with the selection element after the predetermined time has elapsed.
    Type: Application
    Filed: January 26, 2023
    Publication date: April 3, 2025
    Applicant: FUJITSU GENERAL LIMITED
    Inventors: Yasuharu KAWAMURA, Tomoko NAKAMURA, Katsumi OKITA
  • Patent number: 12255127
    Abstract: A semiconductor device that is a surface mount-type device includes a nitride semiconductor chip including a silicon substrate having a first thermal expansion coefficient and an InxGayAl1-x-yN layer in contact with a surface of the silicon substrate, where 0?x?1, 0?y?1, 0?x+y?1; and a die pad including Cu and having a second thermal expansion coefficient that is greater than the first thermal expansion coefficient. A thickness of the nitride semiconductor chip is at least 0.2 mm, length L of the nitride semiconductor chip is at least 3.12 mm, and thickness tm of the die pad and length L of the nitride semiconductor chip satisfy tm?2.00×10?3×L2+0.173, tm being a thickness in mm and L being a length in mm.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: March 18, 2025
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Hidekazu Nakamura, Manabu Yanagihara, Tomohiko Nakamura, Yusuke Katagiri, Katsumi Otani, Takeshi Kawabata
  • Publication number: 20250046525
    Abstract: An electrolytic capacitor with low ESR even in the high frequency range, and the manufacturing method thereof are provided. The solid electrolytic capacitor includes anode foil, a cathode body, and an electrolyte layer. The anode foil id formed of valve action metal, and dielectric oxide film is formed on a surface thereof. The cathode body includes cathode foil formed of valve action metal and a conductive layer formed a surface of the cathode foil. The electrolyte layer intervenes between the anode foil and the cathode foil, and includes electrolytic solution and conductive polymers. The electrolytic solution includes phosphoric acid compound having alkyl groups with the carbon number of 1 to 10.
    Type: Application
    Filed: September 28, 2022
    Publication date: February 6, 2025
    Applicant: Nippon Chemi-Con Corporation
    Inventors: Zhuguang JIN, Takashi MIURA, Yoshiki KAWAI, Katsumi MOGAKI, Kenji MACHIDA, Kenta SATO, Ippei NAKAMURA
  • Publication number: 20250027802
    Abstract: A bubble fraction meter for measuring a bubble fraction of a fluid to be measured, including: an insulator comprising a flow path through which the fluid to be measured flows; a pair of main electrodes disposed at positions facing each other across the flow path in the insulator and configured to measure an electrostatic capacitance of the fluid to be measured in the flow path; a processor including a temperature sensor configured to measure a fluid temperature of the fluid to be measured in the flow path, a pressure sensor configured to measure a pressure of the fluid to be measured in the flow path, and an atmospheric pressure sensor configured to measure an atmospheric pressure, the processor including a fluid relative dielectric constant correction calculation circuit configured to calculate a corrected relative dielectric constant of the fluid to be measured based on the fluid temperature and an absolute fluid pressure which is a value obtained by adding a pressure of the fluid to be measured to the atmo
    Type: Application
    Filed: November 28, 2022
    Publication date: January 23, 2025
    Inventor: Katsumi NAKAMURA
  • Publication number: 20240339500
    Abstract: According to an aspect of the present disclosure, a semiconductor device includes a silicon substrate having a first surface and a second surface opposite the first surface and containing oxygen as impurity, a first electrode provided on the first surface and a second electrode provided on the second surface, wherein the silicon substrate includes an n type drift layer having impurity concentration that is higher on the second surface side, an n type first buffer layer provided on the second surface side of the drift layer and containing protons as impurity, and a second buffer layer provided on the second surface side of the first buffer layer.
    Type: Application
    Filed: October 13, 2023
    Publication date: October 10, 2024
    Applicant: Mitsubishi Electric Corporation
    Inventor: Katsumi NAKAMURA
  • Publication number: 20240274699
    Abstract: A semiconductor device includes a semiconductor substrate, a drift layer of a first conductivity type, a buffer layer of the first conductivity type, a first semiconductor layer, and a second semiconductor layer. The first semiconductor layer and the second semiconductor layer are provided on the side of the second main surface of the semiconductor substrate with respect to the buffer layer. The first semiconductor layer and the second semiconductor layer are arranged in this order in a direction from the second main surface toward the first main surface of the semiconductor substrate. The first semiconductor layer and the second semiconductor layer have conductivity types identical to each other. The second semiconductor layer has a larger number of atoms of impurities per unit volume than the first semiconductor layer.
    Type: Application
    Filed: April 3, 2024
    Publication date: August 15, 2024
    Applicant: Mitsubishi Electric Corporation
    Inventor: Katsumi NAKAMURA
  • Patent number: 12009413
    Abstract: A semiconductor device includes a semiconductor substrate, a drift layer of a first conductivity type, a buffer layer of the first conductivity type, a first semiconductor layer, and a second semiconductor layer. The first semiconductor layer and the second semiconductor layer are provided on the side of the second main surface of the semiconductor substrate with respect to the buffer layer. The first semiconductor layer and the second semiconductor layer are arranged in this order in a direction from the second main surface toward the first main surface of the semiconductor substrate. The first semiconductor layer and the second semiconductor layer have conductivity types identical to each other. The second semiconductor layer has a larger number of atoms of impurities per unit volume than the first semiconductor layer.
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: June 11, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventor: Katsumi Nakamura
  • Publication number: 20240178306
    Abstract: A semiconductor device includes: an N? drift layer of a first conductivity type formed in the semiconductor substrate; a P base layer formed on the N? drift layer; and an N buffer layer of the first conductivity type formed under the N? drift layer and higher in peak impurity concentration than the N? drift layer. The N buffer layer includes: a first buffer layer in which a trap level derived from lattice defect is not detected by a photoluminescence method; and a second buffer layer provided between the first buffer layer and the N? drift layer and in which two types of trap levels derived from lattice defect are detected by the photoluminescence method.
    Type: Application
    Filed: February 5, 2024
    Publication date: May 30, 2024
    Applicant: Mitsubishi Electric Corporation
    Inventor: Katsumi NAKAMURA
  • Publication number: 20240118232
    Abstract: A void fraction sensor according to the present disclosure includes an insulating inner pipe having a through hole through which a low-temperature liquid flows, at least a pair of electrodes mounted on an outer peripheral surface of the insulating inner pipe, and a heat insulating layer covering an outer peripheral side of the insulating inner pipe. A flowmeter according to the present disclosure measures a flow rate of a cryogenic liquid flowing through the through hole of the insulating inner pipe, and includes the void fraction sensor described above, and a flow velocity meter that measures a flow velocity of the cryogenic liquid flowing through the through hole.
    Type: Application
    Filed: December 9, 2021
    Publication date: April 11, 2024
    Inventor: Katsumi NAKAMURA
  • Publication number: 20240110820
    Abstract: A void fraction sensor according to the present disclosure includes an insulating pipe having a through hole through which a cryogenic liquid flows, and a pair of planar electrodes mounted on an outer wall surface of the insulating pipe. The insulating pipe has electrode mounting portions at which a distance D1 between inner wall surfaces in a direction perpendicular to electrode surfaces of the pair of planar electrodes is shorter than a distance D2 between inner wall surfaces in a direction parallel to the electrode surfaces of the pair of planar electrodes.
    Type: Application
    Filed: January 27, 2022
    Publication date: April 4, 2024
    Inventor: Katsumi NAKAMURA
  • Patent number: 11949007
    Abstract: A semiconductor device includes: an N? drift layer of a first conductivity type formed in the semiconductor substrate; a P base layer formed on the N? drift layer; and an N buffer layer of the first conductivity type formed under the N? drift layer and higher in peak impurity concentration than the N? drift layer. The N buffer layer includes: a first buffer layer in which a trap level derived from lattice defect is not detected by a photoluminescence method; and a second buffer layer provided between the first buffer layer and the N? drift layer and in which two types of trap levels derived from lattice defect are detected by the photoluminescence method.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: April 2, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventor: Katsumi Nakamura
  • Publication number: 20240027386
    Abstract: A void fraction sensor for measuring a void fraction of a cryogenic liquid includes a pipe having a flow channel in which a cryogenic liquid flows, a first electrode and a second electrode disposed outside the flow channel, and at least one intermediate electrode disposed in the flow channel and between the first electrode and the second electrode, the at least one intermediate electrode measuring capacitance with the first electrode and/or the second electrode.
    Type: Application
    Filed: December 9, 2021
    Publication date: January 25, 2024
    Inventor: Katsumi NAKAMURA
  • Publication number: 20240027387
    Abstract: A void fraction sensor for measuring a void fraction of a cryogenic liquid includes a pipe having a conduit in which the cryogenic liquid flows, and an electrode provided on the outer peripheral surface of the pipe to measure capacitance of the cryogenic liquid flowing in the conduit. The pipe is composed of an even number of dividable ceramic members, and among the even number of ceramic members, at least two ceramic members facing each other are each provided with the electrode.
    Type: Application
    Filed: December 9, 2021
    Publication date: January 25, 2024
    Inventor: Katsumi NAKAMURA
  • Publication number: 20230369515
    Abstract: In a power semiconductor device, the present disclosure is intended to control tradeoff characteristics while realizing operation in a high-speed side range of the tradeoff characteristics without depending on a carrier lifetime control technique. An n+ cathode layer includes a first n+ cathode layer contacting a second metal layer, and a second n+ cathode layer provided between the first n+ cathode layer and an n buffer layer while contacting the first n+ cathode layer and the n buffer layer. Crystal defect density in the first n+ cathode layer is higher than crystal defect density in the second n+ cathode layer. The n+ cathode layer is absent in an intermediate region and a terminal region.
    Type: Application
    Filed: February 10, 2023
    Publication date: November 16, 2023
    Applicant: Mitsubishi Electric Corporation
    Inventor: Katsumi NAKAMURA
  • Publication number: 20230369477
    Abstract: A semiconductor device includes: a drift layer of a first conduction type provided in a semiconductor substrate having a first principal plane and a second principal plane opposed to the first principal plane; a first semiconductor layer of a second conduction type provided between the first principal plane of the semiconductor substrate and the drift layer and having impurity concentration higher than impurity concentration of the drift layer; a first buffer layer of a first conduction type provided between the second principal plane of the semiconductor substrate and the drift layer and having hydrogen-induced donors with impurity concentration higher than impurity concentration of the drift layer; and a second semiconductor layer of a first conduction type or a second conduction type provided between the second principal plane of the semiconductor substrate and the first buffer layer and having impurity concentration higher than impurity concentration of the drift layer, wherein the first buffer layer incl
    Type: Application
    Filed: July 27, 2023
    Publication date: November 16, 2023
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kakeru OTSUKA, Hayato OKAMOTO, Katsumi NAKAMURA, Koji TANAKA, Koichi NISHI
  • Patent number: 11799022
    Abstract: A semiconductor device includes: a drift layer of a first conduction type provided in a semiconductor substrate having a first principal plane and a second principal plane opposed to the first principal plane; a first semiconductor layer of a second conduction type provided between the first principal plane of the semiconductor substrate and the drift layer and having impurity concentration higher than impurity concentration of the drift layer; a first buffer layer of a first conduction type provided between the second principal plane of the semiconductor substrate and the drift layer and having hydrogen-induced donors with impurity concentration higher than impurity concentration of the drift layer; and a second semiconductor layer of a first conduction type or a second conduction type provided between the second principal plane of the semiconductor substrate and the first buffer layer and having impurity concentration higher than impurity concentration of the drift layer, wherein the first buffer layer incl
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: October 24, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kakeru Otsuka, Hayato Okamoto, Katsumi Nakamura, Koji Tanaka, Koichi Nishi
  • Publication number: 20230335420
    Abstract: A crack generated on a main surface of a substrate is detected, and the main surface of the substrate is scanned with the laser light in order that a time integral of a light amount of laser light for annealing with which a unit area in a crack region including the detected crack is irradiated is smaller than a time integral of a light amount of the laser light with which a unit area in a region different from the crack region is irradiated, to perform laser annealing treatment on the substrate.
    Type: Application
    Filed: March 1, 2023
    Publication date: October 19, 2023
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kazuaki MIKAMI, Tomohiro ISHII, Katsumi NAKAMURA, Kazunori KANADA
  • Patent number: 11780091
    Abstract: To provide a robot control system and a robot control method capable of placing a component grasped by a robot hand at an accurate location on another member. A robot control system is provided with: a robot hand configured to grasp a clip; a camera configured to capture an image of the clip grasped by the robot hand, a calculation unit configured to calculate a position of the clip or an inclination of a component based on an imaging result of the clip captured by the camera, and a robot control unit configured to control the robot hand to adjust, based on the position of the clip or the inclination of the component calculated by the calculation unit, a position or an inclination of the robot hand and move the clip to a stringer.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: October 10, 2023
    Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Akira Kono, Takuya Goto, Takeshi Yamada, Katsumi Nakamura, Kazuto Nakamura, Kenichi Tsuruda, Takahiro Inagaki