Patents by Inventor Katsumi Nakamura
Katsumi Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11545564Abstract: A semiconductor device includes an N-type drift layer provided between a first main surface and a second main surface of the semiconductor substrate and an N-type buffer layer provided between the N-type drift layer and the first main surface and having a higher impurity peak concentration than the N-type drift layer. The N-type buffer layer has a structure that a first buffer layer, a second buffer layer, a third buffer layer, and a fourth buffer layer are disposed in this order from a side of the first main surface. When a distance from an impurity peak position of the first buffer layer to an impurity peak position of the second buffer layer is L12 and a distance from an impurity peak position of the second buffer layer to an impurity peak position of the third buffer layer is L23, a relationship of L23/L12?3.5 is satisfied.Type: GrantFiled: June 1, 2021Date of Patent: January 3, 2023Assignee: Mitsubishi Electric CorporationInventors: Kenji Suzuki, Koichi Nishi, Katsumi Nakamura, Ze Chen, Koji Tanaka
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Publication number: 20220302289Abstract: Hysteresis of gate leakage is reduced in a semiconductor device with a structure including embedded electrodes below gate trench electrodes. A semiconductor device includes an active trench gate formed in a trench coming in contact with an emitter layer, a base layer, and a carrier storage layer to reach a drift layer. The active trench gate includes: a gate trench insulating film formed on an inner wall of the trench; and a gate trench electrode, and an embedded electrode below the gate trench electrode, the gate trench electrode and the embedded electrode being formed on the gate trench insulating film in the trench and being insulated from each other. The embedded electrode is lower in phosphorus concentration than the gate trench electrode.Type: ApplicationFiled: January 4, 2022Publication date: September 22, 2022Applicant: Mitsubishi Electric CorporationInventors: Koichi NISHI, Shinya SONEDA, Akihiko FURUKAWA, Katsumi NAKAMURA
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Patent number: 11444157Abstract: An object is to provide a technique of improving productivity of a semiconductor device. A first buffer layer includes a first portion located in a thickness direction of a semiconductor substrate from a main surface and having a first peak of an N type impurity concentration and a second portion located farther away from the main surface than the first portion and having a second peak of an N type impurity concentration. A distance from the main surface to the first portion is equal to or smaller than 4.0 ?m, and a distance from the first portion to the second portion is equal to or larger than 14.5 ?m. An N type impurity concentration of a portion between the first portion and the second portion is higher than an N type impurity concentration of a drift layer.Type: GrantFiled: October 14, 2020Date of Patent: September 13, 2022Assignee: Mitsubishi Electric CorporationInventors: Kenji Suzuki, Koichi Nishi, Katsumi Nakamura
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Publication number: 20220285537Abstract: A semiconductor device includes a semiconductor substrate, a drift layer of a first conductivity type, a buffer layer of the first conductivity type, a first semiconductor layer, and a second semiconductor layer. The first semiconductor layer and the second semiconductor layer are provided on the side of the second main surface of the semiconductor substrate with respect to the buffer layer. The first semiconductor layer and the second semiconductor layer are arranged in this order in a direction from the second main surface toward the first main surface of the semiconductor substrate. The first semiconductor layer and the second semiconductor layer have conductivity types identical to each other. The second semiconductor layer has a larger number of atoms of impurities per unit volume than the first semiconductor layer.Type: ApplicationFiled: December 2, 2021Publication date: September 8, 2022Applicant: Mitsubishi Electric CorporationInventor: Katsumi NAKAMURA
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Publication number: 20220262638Abstract: A semiconductor device according to the present disclosure includes: a semiconductor substrate with a first main surface and a second main surface; a drift layer of a first conductivity type formed in the semiconductor substrate; a first impurity diffusion layer of a second conductivity type formed on the drift layer to be closer to the first main surface; and a buffer layer of the first conductivity type formed on the drift layer to be closer to the second main surface and higher in peak impurity concentration than the drift layer. The drift layer has a first trap, a second trap, and a third trap, whose energy level each is lower than energy at a bottom of a conduction band by 0.246 eV, 0.349 eV, and 0.470 eV. The second trap has trap density of equal to or greater than 2.0×1011 cm?3.Type: ApplicationFiled: November 9, 2021Publication date: August 18, 2022Applicant: Mitsubishi Electric CorporationInventor: Katsumi NAKAMURA
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Publication number: 20220154768Abstract: A plain bearing includes: a bearing body; a radial bearing portion arranged on an inner peripheral surface of the bearing body; a thrust bearing portion arranged on an axial end surface of the bearing body; a damper portion arranged on an outer peripheral surface of the bearing body; a dam portion arranged on the outer peripheral surface of the bearing body; and an oil hole having an inlet that opens to at least one of the outer peripheral surface of the bearing body and the dam portion, and an outlet that opens to the inner peripheral surface of the bearing body. The inlet, at least a part of the dam portion, and the damper portion are arranged in this order from an axially inner side toward an axially outer side. An outlet of an upstream side oil passage is connected to the inlet on a radially outer side.Type: ApplicationFiled: December 25, 2019Publication date: May 19, 2022Applicant: TAIHO KOGYO CO., LTD.Inventors: Katsumi NAKAMURA, Kazunori NAKAYA, Kazuma HARADA
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Publication number: 20220140118Abstract: A semiconductor device includes: an N? drift layer of a first conductivity type formed in the semiconductor substrate; a P base layer formed on the N? drift layer; and an N buffer layer of the first conductivity type formed under the N? drift layer and higher in peak impurity concentration than the N? drift layer. The N buffer layer includes: a first buffer layer in which a trap level derived from lattice defect is not detected by a photoluminescence method; and a second buffer layer provided between the first buffer layer and the N? drift layer and in which two types of trap levels derived from lattice defect are detected by the photoluminescence method.Type: ApplicationFiled: August 18, 2021Publication date: May 5, 2022Applicant: Mitsubishi Electric CorporationInventor: Katsumi NAKAMURA
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Publication number: 20220115522Abstract: A semiconductor device includes: a drift layer of a first conduction type provided in a semiconductor substrate having a first principal plane and a second principal plane opposed to the first principal plane; a first semiconductor layer of a second conduction type provided between the first principal plane of the semiconductor substrate and the drift layer and having impurity concentration higher than impurity concentration of the drift layer; a first buffer layer of a first conduction type provided between the second principal plane of the semiconductor substrate and the drift layer and having hydrogen-induced donors with impurity concentration higher than impurity concentration of the drift layer; and a second semiconductor layer of a first conduction type or a second conduction type provided between the second principal plane of the semiconductor substrate and the first buffer layer and having impurity concentration higher than impurity concentration of the drift layer, wherein the first buffer layer inclType: ApplicationFiled: April 28, 2021Publication date: April 14, 2022Applicant: Mitsubishi Electric CorporationInventors: Kakeru OTSUKA, Hayato OKAMOTO, Katsumi NAKAMURA, Koji TANAKA, Koichi NISHI
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Publication number: 20220059681Abstract: A semiconductor device includes an N-type drift layer provided between a first main surface and a second main surface of the semiconductor substrate and an N-type buffer layer provided between the N-type drift layer and the first main surface and having a higher impurity peak concentration than the N-type drift layer. The N-type buffer layer has a structure that a first buffer layer, a second buffer layer, a third buffer layer, and a fourth buffer layer are disposed in this order from a side of the first main surface. When a distance from an impurity peak position of the first buffer layer to an impurity peak position of the second buffer layer is L12 and a distance from an impurity peak position of the second buffer layer to an impurity peak position of the third buffer layer is L23, a relationship of L23/L12?3.5 is satisfied.Type: ApplicationFiled: June 1, 2021Publication date: February 24, 2022Applicant: Mitsubishi Electric CorporationInventors: Kenji SUZUKI, Koichi NISHI, Katsumi NAKAMURA, Ze CHEN, Koji TANAKA
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Patent number: 11198520Abstract: The object is to provide an aircraft component positioning device, an aircraft assembly system, and an aircraft assembly method with which it is possible to precisely dispose components on a planar member of an aircraft without using a positioning jig. A positioning device (2) includes a detection unit (5) that detects positions of a plurality of first components installed on a planar member of an aircraft, a virtual position creation unit (6) that creates a virtual position between the plurality of first components on the basis of the positions of the plurality of first components that are detected, and a position determination unit (7) that, on the basis of the virtual position that is created, determines an installation position of a second component, different from the plurality of first components, that is installed on the planar member.Type: GrantFiled: January 27, 2016Date of Patent: December 14, 2021Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.Inventors: Takuya Goto, Tsuyoshi Kaneko, Hiroto Mori, Michinobu Takahagi, Hideyuki Suzuki, Junichi Takeshita, Jiro Wada, Katsumi Nakamura
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Publication number: 20210273053Abstract: An object is to provide a technique of improving productivity of a semiconductor device. A first buffer layer includes a first portion located in a thickness direction of a semiconductor substrate from a main surface and having a first peak of an N type impurity concentration and a second portion located farther away from the main surface than the first portion and having a second peak of an N type impurity concentration. A distance from the main surface to the first portion is equal to or smaller than 4.0 ?m, and a distance from the first portion to the second portion is equal to or larger than 14.5 ?m. An N type impurity concentration of a portion between the first portion and the second portion is higher than an N type impurity concentration of a drift layer.Type: ApplicationFiled: October 14, 2020Publication date: September 2, 2021Applicant: Mitsubishi Electric CorporationInventors: Kenji SUZUKI, Koichi NISHI, Katsumi NAKAMURA
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Patent number: 11101133Abstract: An object of the present invention is to provide stable withstand voltage characteristics, reduce turn-off losses along with a reduction in leakage current when the device is off, improve controllability of turn-off operations, and improve blocking capability at turn-off. An N buffer layer includes a first buffer layer joined to an active layer and having one peak in impurity concentration, and a second buffer layer joined to the first buffer layer and an N? drift layer, having at least one peak point in impurity concentration, and having a lower maximum impurity concentration than the first buffer layer. The impurity concentration at the peak point of the first buffer layer is higher than the impurity concentration of the N? drift layer, and the impurity concentration of the second buffer layer is higher than the impurity concentration of the N? drift layer in the entire area of the second buffer layer.Type: GrantFiled: June 21, 2019Date of Patent: August 24, 2021Assignee: Mitsubishi Electric CorporationInventor: Katsumi Nakamura
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Patent number: 10950461Abstract: A semiconductor device of the present invention includes a substrate having a drift layer, metal wiring formed on an upper surface of the substrate, and an electrode formed on a back surface of the substrate, wherein the lifetime of carriers in the drift layer satisfies the following expression 1: [Expression 1] ??1.5×10?5 exp(5.4×103tN?)??expression 1 ?: the lifetime of carriers in the drift layer tN?: the layer thickness of the drift layer.Type: GrantFiled: September 27, 2019Date of Patent: March 16, 2021Assignee: Mitsubishi Electric CorporationInventor: Katsumi Nakamura
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Patent number: 10916444Abstract: A semiconductor device of the present invention includes a substrate having a drift layer, metal wiring formed on an upper surface of the substrate, and an electrode formed on a back surface of the substrate, wherein the lifetime of carriers in the drift layer satisfies the following expression 1: [Expression 1] ??1.5×10?5 exp(5.4×103tN?)??expression 1 ?: the lifetime of carriers in the drift layer tN?: the layer thickness of the drift layer.Type: GrantFiled: September 27, 2019Date of Patent: February 9, 2021Assignee: Mitsubishi Electric CorporationInventor: Katsumi Nakamura
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Patent number: 10903312Abstract: A semiconductor device includes a semiconductor substrate in which an active region and an edge termination region are defined, a semiconductor element formed in the active region, and first to fourth P layers formed in a region spanning from an edge portion of the active region to the edge termination region in the surface of the semiconductor substrate. The first to fourth P layers respectively have surface concentrations P(1) to P(4) that decrease in this order, bottom-end distances D(1) to D(4) that increase in this order, and distances B(1) to B(4) to the edge of the semiconductor substrate that increase in this order. The surface concentration P(4) is 10 to 1000 times the impurity concentration of the semiconductor substrate, and the bottom-end distance D(4) is in the range of 15 to 30 ?m.Type: GrantFiled: October 22, 2019Date of Patent: January 26, 2021Assignee: Mitsubishi Electric CorporationInventors: Ze Chen, Katsumi Nakamura
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Patent number: 10814488Abstract: To hold a long member in the original shape of the long member at a precise position, a long member assembling device has: a plurality of hand parts configured to grip a long member; arm parts and trunk parts configured to move the hand parts to adjust the positions of the plurality of hand parts gripping the long member; a storage unit in which the original shape of the long member is stored; and a control unit configured to, on the basis of the original shape of the long member stored in the storage unit, drive the arm parts and the trunk parts to adjust the positions of the plurality of hand parts gripping the long member such that the shape of the long member gripped by the plurality of hand parts matches the original shape of the long member stored in the storage unit.Type: GrantFiled: July 19, 2016Date of Patent: October 27, 2020Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.Inventors: Toshihiro Tombe, Takuya Goto, Takahiro Inagaki, Makoto Hirai, Naoki Goto, Masanobu Mizukami, Katsumi Nakamura
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Patent number: 10749043Abstract: A semiconductor device having first through third layers. The first layer has a first conductivity type. The second layer has a second conductivity type different from the first conductivity type. The third layer has a first portion having the second conductivity type and a second portion having the first conductivity type. A trench structure is located in the first portion and is completely surrounded by the first portion in an area extending from a first surface of the third layer to a second surface of the third layer.Type: GrantFiled: September 14, 2017Date of Patent: August 18, 2020Assignee: MITSUBISHI ELECTRIC CORPORATIONInventor: Katsumi Nakamura
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Publication number: 20200171665Abstract: To provide a robot control system and a robot control method capable of placing a component grasped by a robot hand at an accurate location on another member. A robot control system is provided with: a robot hand configured to grasp a clip; a camera configured to capture an image of the clip grasped by the robot hand, a calculation unit configured to calculate a position of the clip or an inclination of a component based on an imaging result of the clip captured by the camera, and a robot control unit configured to control the robot hand to adjust, based on the position of the clip or the inclination of the component calculated by the calculation unit, a position or an inclination of the robot hand and move the clip to a stringer.Type: ApplicationFiled: June 8, 2017Publication date: June 4, 2020Inventors: Akira KONO, Takuya GOTO, Takeshi YAMADA, Katsumi NAKAMURA, Kazuto NAKAMURA, Kenichi TSURUDA, Takahiro INAGAKI
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Patent number: 10668583Abstract: In order to hold a long member without using a fixing jig and without deforming the long member in holding the long member, a long member assembling device is provided with: multiple hand parts for gripping a long member; and arm parts and trunk parts for moving the hand parts to adjust the positions of the hand parts gripping the long member. The hand parts have a configuration such that, when the positions thereof are adjusted by the arm parts and the trunk parts, the hand parts are capable of moving in the longitudinal direction of the long member while gripping the long member.Type: GrantFiled: July 27, 2016Date of Patent: June 2, 2020Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.Inventors: Takahiro Inagaki, Toshihiro Tombe, Takuya Goto, Makoto Hirai, Naoki Goto, Masanobu Mizukami, Katsumi Nakamura
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Patent number: 10665677Abstract: The present invention relates to a vertical semiconductor device such as an IGBT or a diode which includes an N buffer layer formed in the undersurface of and adjacent to an N? drift layer. A concentration slope ?, which is derived from displacements in a depth TB (?m) and an impurity concentration CB (cm?3), from the upper surface to the lower surface in a main portion of the N buffer layer satisfies a concentration slope condition defined by {0.03???0.7}.Type: GrantFiled: December 11, 2018Date of Patent: May 26, 2020Assignee: Mitsubishi Electric CorporationInventor: Katsumi Nakamura