Patents by Inventor Katsumi Nakamura

Katsumi Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220140118
    Abstract: A semiconductor device includes: an N? drift layer of a first conductivity type formed in the semiconductor substrate; a P base layer formed on the N? drift layer; and an N buffer layer of the first conductivity type formed under the N? drift layer and higher in peak impurity concentration than the N? drift layer. The N buffer layer includes: a first buffer layer in which a trap level derived from lattice defect is not detected by a photoluminescence method; and a second buffer layer provided between the first buffer layer and the N? drift layer and in which two types of trap levels derived from lattice defect are detected by the photoluminescence method.
    Type: Application
    Filed: August 18, 2021
    Publication date: May 5, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventor: Katsumi NAKAMURA
  • Publication number: 20220115522
    Abstract: A semiconductor device includes: a drift layer of a first conduction type provided in a semiconductor substrate having a first principal plane and a second principal plane opposed to the first principal plane; a first semiconductor layer of a second conduction type provided between the first principal plane of the semiconductor substrate and the drift layer and having impurity concentration higher than impurity concentration of the drift layer; a first buffer layer of a first conduction type provided between the second principal plane of the semiconductor substrate and the drift layer and having hydrogen-induced donors with impurity concentration higher than impurity concentration of the drift layer; and a second semiconductor layer of a first conduction type or a second conduction type provided between the second principal plane of the semiconductor substrate and the first buffer layer and having impurity concentration higher than impurity concentration of the drift layer, wherein the first buffer layer incl
    Type: Application
    Filed: April 28, 2021
    Publication date: April 14, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kakeru OTSUKA, Hayato OKAMOTO, Katsumi NAKAMURA, Koji TANAKA, Koichi NISHI
  • Publication number: 20220059681
    Abstract: A semiconductor device includes an N-type drift layer provided between a first main surface and a second main surface of the semiconductor substrate and an N-type buffer layer provided between the N-type drift layer and the first main surface and having a higher impurity peak concentration than the N-type drift layer. The N-type buffer layer has a structure that a first buffer layer, a second buffer layer, a third buffer layer, and a fourth buffer layer are disposed in this order from a side of the first main surface. When a distance from an impurity peak position of the first buffer layer to an impurity peak position of the second buffer layer is L12 and a distance from an impurity peak position of the second buffer layer to an impurity peak position of the third buffer layer is L23, a relationship of L23/L12?3.5 is satisfied.
    Type: Application
    Filed: June 1, 2021
    Publication date: February 24, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kenji SUZUKI, Koichi NISHI, Katsumi NAKAMURA, Ze CHEN, Koji TANAKA
  • Patent number: 11198520
    Abstract: The object is to provide an aircraft component positioning device, an aircraft assembly system, and an aircraft assembly method with which it is possible to precisely dispose components on a planar member of an aircraft without using a positioning jig. A positioning device (2) includes a detection unit (5) that detects positions of a plurality of first components installed on a planar member of an aircraft, a virtual position creation unit (6) that creates a virtual position between the plurality of first components on the basis of the positions of the plurality of first components that are detected, and a position determination unit (7) that, on the basis of the virtual position that is created, determines an installation position of a second component, different from the plurality of first components, that is installed on the planar member.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: December 14, 2021
    Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Takuya Goto, Tsuyoshi Kaneko, Hiroto Mori, Michinobu Takahagi, Hideyuki Suzuki, Junichi Takeshita, Jiro Wada, Katsumi Nakamura
  • Publication number: 20210273053
    Abstract: An object is to provide a technique of improving productivity of a semiconductor device. A first buffer layer includes a first portion located in a thickness direction of a semiconductor substrate from a main surface and having a first peak of an N type impurity concentration and a second portion located farther away from the main surface than the first portion and having a second peak of an N type impurity concentration. A distance from the main surface to the first portion is equal to or smaller than 4.0 ?m, and a distance from the first portion to the second portion is equal to or larger than 14.5 ?m. An N type impurity concentration of a portion between the first portion and the second portion is higher than an N type impurity concentration of a drift layer.
    Type: Application
    Filed: October 14, 2020
    Publication date: September 2, 2021
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kenji SUZUKI, Koichi NISHI, Katsumi NAKAMURA
  • Patent number: 11101133
    Abstract: An object of the present invention is to provide stable withstand voltage characteristics, reduce turn-off losses along with a reduction in leakage current when the device is off, improve controllability of turn-off operations, and improve blocking capability at turn-off. An N buffer layer includes a first buffer layer joined to an active layer and having one peak in impurity concentration, and a second buffer layer joined to the first buffer layer and an N? drift layer, having at least one peak point in impurity concentration, and having a lower maximum impurity concentration than the first buffer layer. The impurity concentration at the peak point of the first buffer layer is higher than the impurity concentration of the N? drift layer, and the impurity concentration of the second buffer layer is higher than the impurity concentration of the N? drift layer in the entire area of the second buffer layer.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: August 24, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Katsumi Nakamura
  • Patent number: 10950461
    Abstract: A semiconductor device of the present invention includes a substrate having a drift layer, metal wiring formed on an upper surface of the substrate, and an electrode formed on a back surface of the substrate, wherein the lifetime of carriers in the drift layer satisfies the following expression 1: [Expression 1] ??1.5×10?5 exp(5.4×103tN?)??expression 1 ?: the lifetime of carriers in the drift layer tN?: the layer thickness of the drift layer.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: March 16, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Katsumi Nakamura
  • Patent number: 10916444
    Abstract: A semiconductor device of the present invention includes a substrate having a drift layer, metal wiring formed on an upper surface of the substrate, and an electrode formed on a back surface of the substrate, wherein the lifetime of carriers in the drift layer satisfies the following expression 1: [Expression 1] ??1.5×10?5 exp(5.4×103tN?)??expression 1 ?: the lifetime of carriers in the drift layer tN?: the layer thickness of the drift layer.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: February 9, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Katsumi Nakamura
  • Patent number: 10903312
    Abstract: A semiconductor device includes a semiconductor substrate in which an active region and an edge termination region are defined, a semiconductor element formed in the active region, and first to fourth P layers formed in a region spanning from an edge portion of the active region to the edge termination region in the surface of the semiconductor substrate. The first to fourth P layers respectively have surface concentrations P(1) to P(4) that decrease in this order, bottom-end distances D(1) to D(4) that increase in this order, and distances B(1) to B(4) to the edge of the semiconductor substrate that increase in this order. The surface concentration P(4) is 10 to 1000 times the impurity concentration of the semiconductor substrate, and the bottom-end distance D(4) is in the range of 15 to 30 ?m.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: January 26, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ze Chen, Katsumi Nakamura
  • Patent number: 10814488
    Abstract: To hold a long member in the original shape of the long member at a precise position, a long member assembling device has: a plurality of hand parts configured to grip a long member; arm parts and trunk parts configured to move the hand parts to adjust the positions of the plurality of hand parts gripping the long member; a storage unit in which the original shape of the long member is stored; and a control unit configured to, on the basis of the original shape of the long member stored in the storage unit, drive the arm parts and the trunk parts to adjust the positions of the plurality of hand parts gripping the long member such that the shape of the long member gripped by the plurality of hand parts matches the original shape of the long member stored in the storage unit.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: October 27, 2020
    Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Toshihiro Tombe, Takuya Goto, Takahiro Inagaki, Makoto Hirai, Naoki Goto, Masanobu Mizukami, Katsumi Nakamura
  • Patent number: 10749043
    Abstract: A semiconductor device having first through third layers. The first layer has a first conductivity type. The second layer has a second conductivity type different from the first conductivity type. The third layer has a first portion having the second conductivity type and a second portion having the first conductivity type. A trench structure is located in the first portion and is completely surrounded by the first portion in an area extending from a first surface of the third layer to a second surface of the third layer.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: August 18, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Katsumi Nakamura
  • Publication number: 20200171665
    Abstract: To provide a robot control system and a robot control method capable of placing a component grasped by a robot hand at an accurate location on another member. A robot control system is provided with: a robot hand configured to grasp a clip; a camera configured to capture an image of the clip grasped by the robot hand, a calculation unit configured to calculate a position of the clip or an inclination of a component based on an imaging result of the clip captured by the camera, and a robot control unit configured to control the robot hand to adjust, based on the position of the clip or the inclination of the component calculated by the calculation unit, a position or an inclination of the robot hand and move the clip to a stringer.
    Type: Application
    Filed: June 8, 2017
    Publication date: June 4, 2020
    Inventors: Akira KONO, Takuya GOTO, Takeshi YAMADA, Katsumi NAKAMURA, Kazuto NAKAMURA, Kenichi TSURUDA, Takahiro INAGAKI
  • Patent number: 10668583
    Abstract: In order to hold a long member without using a fixing jig and without deforming the long member in holding the long member, a long member assembling device is provided with: multiple hand parts for gripping a long member; and arm parts and trunk parts for moving the hand parts to adjust the positions of the hand parts gripping the long member. The hand parts have a configuration such that, when the positions thereof are adjusted by the arm parts and the trunk parts, the hand parts are capable of moving in the longitudinal direction of the long member while gripping the long member.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: June 2, 2020
    Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Takahiro Inagaki, Toshihiro Tombe, Takuya Goto, Makoto Hirai, Naoki Goto, Masanobu Mizukami, Katsumi Nakamura
  • Patent number: 10665677
    Abstract: The present invention relates to a vertical semiconductor device such as an IGBT or a diode which includes an N buffer layer formed in the undersurface of and adjacent to an N? drift layer. A concentration slope ?, which is derived from displacements in a depth TB (?m) and an impurity concentration CB (cm?3), from the upper surface to the lower surface in a main portion of the N buffer layer satisfies a concentration slope condition defined by {0.03???0.7}.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: May 26, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Katsumi Nakamura
  • Patent number: 10654138
    Abstract: A production facility is provided with: an AGV for transporting a plurality of fuselage panels of multiple types having different shapes in a mixed state on a previously determined transport path; a plurality of A/Rs for riveting the fuselage panels; work areas set so as to correspond to the respective A/Rs in which the A/Rs move to rivet the fuselage panels; and a buffer area, set beforehand in the transport path adjacent to the work area, to which the A/R corresponding to the adjacent work area moves so as to rivet the fuselage panel. When there is no fuselage panel to be riveted in the work area adjacent to the buffer area and the fuselage panel to be riveted is present in the buffer area, a control device moves the A/R corresponding to the work area adjacent to the buffer area to the buffer area to rivet the fuselage panel.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: May 19, 2020
    Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Makoto Hirai, Takuya Goto, Tsuyoshi Kaneko, Katsumi Nakamura
  • Publication number: 20200058506
    Abstract: An object of the present invention is to provide stable withstand voltage characteristics, reduce turn-off losses along with a reduction in leakage current when the device is off, improve controllability of turn-off operations, and improve blocking capability at turn-off. An N buffer layer includes a first buffer layer joined to an active layer and having one peak in impurity concentration, and a second buffer layer joined to the first buffer layer and an N? drift layer, having at least one peak point in impurity concentration, and having a lower maximum impurity concentration than the first buffer layer. The impurity concentration at the peak point of the first buffer layer is higher than the impurity concentration of the N? drift layer, and the impurity concentration of the second buffer layer is higher than the impurity concentration of the N? drift layer in the entire area of the second buffer layer.
    Type: Application
    Filed: June 21, 2019
    Publication date: February 20, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventor: Katsumi NAKAMURA
  • Publication number: 20200052065
    Abstract: A semiconductor device includes a semiconductor substrate in which an active region and an edge termination region are defined, a semiconductor element formed in the active region, and first to fourth P layers formed in a region spanning from an edge portion of the active region to the edge termination region in the surface of the semiconductor substrate. The first to fourth P layers respectively have surface concentrations P(1) to P(4) that decrease in this order, bottom-end distances D(1) to D(4) that increase in this order, and distances B(1) to B(4) to the edge of the semiconductor substrate that increase in this order. The surface concentration P(4) is 10 to 1000 times the impurity concentration of the semiconductor substrate, and the bottom-end distance D(4) is in the range of 15 to 30 ?m.
    Type: Application
    Filed: October 22, 2019
    Publication date: February 13, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Ze CHEN, Katsumi NAKAMURA
  • Publication number: 20200027748
    Abstract: A semiconductor device of the present invention includes a substrate having a drift layer, metal wiring formed on an upper surface of the substrate, and an electrode formed on a back surface of the substrate, wherein the lifetime of carriers in the drift layer satisfies the following expression 1: [Expression 1] ??1.5×10?5exp(5.4×103tN?)??expression 1 ?: the lifetime of carriers in the drift layer tN?: the layer thickness of the drift layer.
    Type: Application
    Filed: September 27, 2019
    Publication date: January 23, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventor: Katsumi NAKAMURA
  • Patent number: 10514208
    Abstract: Provided is a heat storage including a container including a first container made of ceramics and a second container made of ceramics, the first container and the second container being combined, and a heat storage material housed inside the container. The first container and the second container are bonded via a bonding member. A volume occupied by pores in the first container, in a first contact region including a surface section in contact with the bonding member, is greater than a volume occupied by pores in regions other than the first contact region. A volume occupied by pores in the second container, in a second contact region including a surface section in contact with the bonding member, is greater than a volume occupied by pores in regions other than the second contact region.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: December 24, 2019
    Assignee: KYOCERA CORPORATION
    Inventors: Hiroshi Hamashima, Katsumi Nakamura
  • Patent number: 10475663
    Abstract: A semiconductor device of the present invention includes a substrate having a drift layer, metal wiring formed on an upper surface of the substrate, and an electrode formed on a back surface of the substrate, wherein the lifetime of carriers in the drift layer satisfies the following expression 1: [Expression 1] ??1.5×10?5exp(5.4×103tN-)??expression 1 ?: the lifetime of carriers in the drift layer tN-: the layer thickness of the drift layer.
    Type: Grant
    Filed: October 2, 2012
    Date of Patent: November 12, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventor: Katsumi Nakamura