Patents by Inventor Katsunori Nakamura

Katsunori Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6470432
    Abstract: In a data processing system in which main and sub disk storage devices are under the control of individual each disk control devices, the write processing time is reduced by selectively sending data according to the command-chaining time between main and sub disk control devices. A section for judging cable length and function of the sub disk control device 36 estimates command-chaining time between a pair of main and sub disk storage devices. The channel command analyzing section 31 estimates the number of records to be transferred and the length of a record using a LOCATE RECORD command. The command judgment section for the sub disk control device 32 optimizes the command-chain to be issued to the sub disk control device using the above-mentioned information. Then, the section for issuing command to the sub disk control device 35 issues the optimized command chain. Thus, a shorter transmission time is realized by either sending individual records or an entire track of data.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: October 22, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Koji Ozawa, Kazuhide Sano, Takeshi Koide, Katsunori Nakamura
  • Publication number: 20020129202
    Abstract: A primary controller operates to transmit write data and a write time to a secondary controller in the earlier sequence of the write times after reporting a completion of a request for write to a processing unit. The secondary controller stores the write data and the write time transmitted from the primary controller in the cache memory. At a time, the secondary controller stores the write data in a disk unit in the earlier sequence of the write time. These operations make it possible to guarantee all the write data on or before the reference time.
    Type: Application
    Filed: May 7, 2002
    Publication date: September 12, 2002
    Inventors: Akira Yamamoto, Katsunori Nakamura, Shigeru Kishiro
  • Patent number: 6408370
    Abstract: A primary controller operates to transmit write data and a write time to a secondary controller in the earlier sequence of the write times after reporting a completion of a request for write to a processing unit. The secondary controller stores the write data and the write time transmitted from the primary controller in the cache memory. At a time, the secondary controller stores the write data in a disk unit in the earlier sequence of the write time. These operations make it possible to guarantee all the write data on or before the reference time.
    Type: Grant
    Filed: September 9, 1998
    Date of Patent: June 18, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Akira Yamamoto, Katsunori Nakamura, Shigeru Kishiro
  • Publication number: 20020062429
    Abstract: There is realized a storage system which can reduce the limitation of a device number used by a host CPU at the time of duplexing data. A micro processor of a source external storage controller unit unifies a plurality of write data received from the host CPU to the same data bus to provide one unit of data transmitting to a target storage system. A number not dependent on the device number used when the host CPU specifies a device is allocated to this. Then, the source external storage controller unit sends the write data to the target external storage controller unit. This can receive/send the data without depending on the target specifying device number.
    Type: Application
    Filed: August 3, 2001
    Publication date: May 23, 2002
    Inventors: Masanao Tsuboki, Masamitsu Takahashi, Katsunori Nakamura, Takahiko Takeda
  • Publication number: 20020046330
    Abstract: With the purpose of achieving consistent non-synchronous copying of data from a plurality of primary side control units to a plurality of secondary side control units, all of the secondary side control units are connected via a loop, and each of the secondary side control units determines guarantee time by circulating a time added to the data received from the primary side control units via said loop communication route. A consistent data copying is guaranteed by circulating the determined guarantee time via the loop communication route.
    Type: Application
    Filed: April 19, 2001
    Publication date: April 18, 2002
    Inventors: Tooru Suzuki, Katsunori Nakamura, Teruo Nagasawa, Takahisa Kimura, Takeshi Koide
  • Patent number: 6374327
    Abstract: A method, apparatus and computer program for controlling data migration in an information processing system which includes a central processing unit (CPU), a new storage system connected to the CPU and an old storage system connected to the new storage system. In the information processing system data migration is conducted to transfer data from the old storage system to the new storage system. The invention operates by permitting access by the CPU to the storage systems during data migration. When an access by the CPU is generated the invention determines whether the access is to a region where data migration has been completed or to a region where data migration has not been completed. If the access is to a region where data migration has been completed, then processing of the access is handled by the new storage system.
    Type: Grant
    Filed: February 14, 2001
    Date of Patent: April 16, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Hidetoshi Sakaki, Akira Kurano, Katsunori Nakamura, Takehiro Ishikawa, Toshiaki Hatanaka, Hiroshi Nishijima
  • Publication number: 20020032834
    Abstract: In a data processing system in which main and sub disk storage devices are under the control of individual each disk control devices, the write processing time is reduced by selectively sending data according to the command-chaining time between main and sub disk control devices. A section for judging cable length and function of the sub disk control device 36 estimates command-chaining time between a pair of main and sub disk storage devices. The channel command analyzing section 31 estimates the number of records to be transferred and the length of a record using a LOCATE RECORD command. The command judgment section for the sub disk control device 32 optimizes the command-chain to be issued to the sub disk control device using the above-mentioned information. Then, the section for issuing command to the sub disk control device 35 issues the optimized command chain. Thus, a shorter transmission time is realized by either sending individual records or an entire track of data.
    Type: Application
    Filed: November 13, 2001
    Publication date: March 14, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Koji Ozawa, Kazuhide Sano, Takeshi Koide, Katsunori Nakamura
  • Publication number: 20020026559
    Abstract: Disk units operable under control of different disk control units hold the same data. Under circumstances in which data is duplexed, when data is duplexed again after data that is generally saved as backup data was accessed for reading and writing, in order to efficiently duplex data, update places of both original data and sub-data updated during the duplexing of data is interrupted are registered on an access information management table of an original disk control unit. When the original disk control unit receives a duplexing resume command, the duplexing of data may be efficiently reorganized by copying original data corresponding to an access place produced during the duplexing is interrupted from information of the access information management table to the backup data or by copying the backup data to the original data.
    Type: Application
    Filed: October 22, 2001
    Publication date: February 28, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Hitoshi Shiozawa, Koji Ozawa, Takahisa Kimura, Kazuhito Suishu, Kosaku Kambayashi, Katsunori Nakamura
  • Publication number: 20020012234
    Abstract: In a semiconductor package which contains an IC element therein and effects the inputting and outputting of a signal to the IC element through a plurality of pads, a group of signals is layout-patterned so as to divided into a plurality of groups such as a group of signals weak against noise, a group of signals liable to discharge noise and a group of signals exchanging a heavy current and so that the groups may be isolated from one another.
    Type: Application
    Filed: September 15, 1998
    Publication date: January 31, 2002
    Inventors: YOSHIHITO HARADA, KATSUNORI NAKAMURA
  • Patent number: 6321292
    Abstract: In a data processing system in which main and sub disk storage devices are under the control of individual each disk control devices, the write processing time is reduced by selectively sending data according to the command-chaining time between main and sub disk control devices. A section for judging cable length and function of the sub disk control device 36 estimates command-chaining time between a pair of main and sub disk storage devices. The channel command analyzing section 31 estimates the number of records to be transferred and the length of a record using a LOCATE RECORD command. The command judgment section for the sub disk control device 32 optimizes the command-chain to be issued to the sub disk control device using the above-mentioned information. Then, the section for issuing command to the sub disk control device 35 issues the optimized command chain. Thus, a shorter transmission time is realized by either sending individual records or an entire track of data.
    Type: Grant
    Filed: August 17, 1999
    Date of Patent: November 20, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Koji Ozawa, Kazuhide Sano, Takeshi Koide, Katsunori Nakamura
  • Publication number: 20010029570
    Abstract: A primary controller operates to transmit write data and a write time to a secondary controller in the earlier sequence of the write times after reporting a completion of a request for write to a processing unit. The secondary controller stores the write data and the write time transmitted from the primary controller in the cache memory. At a time, the secondary controller stores the write data in a disk unit in the earlier sequence of the write time. These operations make it possible to guarantee all the write data on or before the reference time.
    Type: Application
    Filed: September 9, 1998
    Publication date: October 11, 2001
    Inventors: AKIRA YAMAMOTO, KATSUNORI NAKAMURA, SHIGERU KISHIRO
  • Publication number: 20010011324
    Abstract: A method, apparatus and computer program for controlling data migration in an information processing system which includes a central processing unit (CPU), a new storage system connected to the CPU and an old storage system connected to the new storage system. In the information processing system data migration is conducted to transfer data from the old storage system to the new storage system. The invention operates by permitting access by the CPU to the storage systems during data migration. When an access by the CPU is generated the invention determines whether the access is to a region where data migration has been completed or to a region where data migration has not been completed. If the access is to a region where data migration has been completed, then processing of the access is handled by the new storage system.
    Type: Application
    Filed: February 14, 2001
    Publication date: August 2, 2001
    Inventors: Hidetoshi Sakaki, Akira Kurano, Katsunori Nakamura, Takehiro Ishikawa, Toshiaki Hatanaka, Hiroshi Nishijima
  • Patent number: 6240494
    Abstract: In order to enable data migration between old and new subsystems to be performed under stopless operation, a plurality of first access paths are prepared between a CPU and an old CU (old subsystem) having an old VOL and a plurality of third access paths are set between the old CU and a new CU (new subsystem) having a new VOL. The connection is switched from the first access paths of the old subsystem as a replacement source to the second access paths of the new subsystem as a replacement destination on a plurality of occasions. When the CPU accesses the new subsystem via the second access paths on the new subsystem side during the connection change, a path replacement controller relays the access to the old subsystem via the third access paths and allows the access to be processed. Data migration from the old subsystem to the new subsystem is executed after all of the first access paths are switched to the second access paths.
    Type: Grant
    Filed: December 16, 1998
    Date of Patent: May 29, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Teruo Nagasawa, Takeshi Koide, Katsunori Nakamura
  • Patent number: 6230239
    Abstract: A method, apparatus and computer program for controlling data migration in an information processing system which includes a central processing unit (CPU), a new storage system connected to the CPU and an old storage system connected to the new storage system. In the information processing system data migration is conducted to transfer data from the old storage system to the new storage system. The invention operates by permitting access by the CPU to the storage systems during data migration. When an access by the CPU is generated the invention determines whether the access is to a region where data migration has been completed or to a region where data migration has not been completed. If the access is to a region where data migration has been completed, then processing of the access is handled by the new storage system.
    Type: Grant
    Filed: December 11, 1997
    Date of Patent: May 8, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Hidetoshi Sakaki, Akira Kurano, Katsunori Nakamura, Takehiro Ishikawa, Toshiaki Hatanaka, Hiroshi Nishijima
  • Publication number: 20010000818
    Abstract: In order to enable data migration between old and new subsystems to be performed under stopless operation, a plurality of first access paths 20 and 21 are prepared between a CPU 10 and an old CU 13 (old subsystem) having an old VOL 14 and a plurality of third access paths 30 and 31 are set between the old CU 13 and a new CU 11 (new subsystem) having a new VOL 12. The connection is switched from the first access paths 20 and 21 of the old subsystem as a replacement source to the second access paths 20′and 21′of the new subsystem as a replacement destination on a plurality of occasions. When the CPU 10 accesses the new subsystem via the second access paths 20′and 21′ on the new subsystem side during the connection change, a path replacement controller 111 relays the access to the old subsystem via the third access paths 30 and 31 and allows the access to be processed.
    Type: Application
    Filed: December 22, 2000
    Publication date: May 3, 2001
    Inventors: Teruo Nagasawa, Takeshi Koide, Katsunori Nakamura
  • Patent number: 6035139
    Abstract: In a camera in which a sensor receives reflected light from a subject during flash emission to control the amount of flash light emission on the basis of the output of the sensor, a plurality of focus detecting areas are provided within a light-receiving area of the sensor, and when one of the plurality of focus detecting areas is selected for focus adjustment, the camera sets an evaluation criterion for the output of the sensor in accordance with a position of the selected focus detecting area.
    Type: Grant
    Filed: July 27, 1998
    Date of Patent: March 7, 2000
    Assignee: Canon Kabushiki Kaisha
    Inventor: Katsunori Nakamura
  • Patent number: 5978890
    Abstract: In a data processing system in which main and sub disk storage devices are under the control of individual each disk control devices, the write processing time is reduced by selectively sending data according to the command-chaining time between main and sub disk control devices. A section for judging cable length and function of the sub disk control device 36 estimates command-chaining time between a pair of main and sub disk storage devices. The channel command analyzing section 31 estimates the number of records to be transferred and the length of a record using a LOCATE RECORD command. The command judgment section for the sub disk control device 32 optimizes the command-chain to be issued to the sub disk control device using the above-mentioned information. Then, the section for issuing command to the sub disk control device 35 issues the optimized command chain. Thus, a shorter transmission time is realized by either sending individual records or an entire track of data.
    Type: Grant
    Filed: January 8, 1997
    Date of Patent: November 2, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Koji Ozawa, Kazuhide Sano, Takeshi Koide, Katsunori Nakamura
  • Patent number: 5970258
    Abstract: The present invention provides a conveniently usable optical apparatus such as a camera which is provided with a visual axis detecting apparatus and a display portion in the field of view of a finder and which realizes a predetermined operating function which is not started when the finder observer is seeing the display portion and the like.
    Type: Grant
    Filed: March 17, 1997
    Date of Patent: October 19, 1999
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuo Suda, Katsunori Nakamura
  • Patent number: 5632250
    Abstract: Supply of fuel is stopped when fuel pressure sensed by a pressure sensor provided upstream of a regulator is at a predetermined value or less to avoid abnormal combustion caused by improper adjustment of air/fuel ratio. Even slight variation of the fuel pressure is sensed by monitoring the fuel pressure in an interval after closing a fuel shut-off valve once opened to re-opening of it. In addition, an abnormal state in the fuel system is detected by comparing an accumulated value of amount of injected fuel and an estimated value of fuel consumption in the tank. Furthermore, the peak current value of the fuel injection valve is controlled so that, when the engine at a low temperature is started, lift load of the injection valve is larger than sticking force of the injection valve, thereby preventing such situation where the injection valve is frozen so that it cannot supply fuel to the engine. In this case, the engine can be smoothly started by simultaneously controlling the valve open time.
    Type: Grant
    Filed: September 19, 1995
    Date of Patent: May 27, 1997
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Atsushi Kato, Yoshikazu Ohshima, Eisaku Gosho, Kazuhiro Ueda, Shigeo Hidai, Akira Murakami, Toshiyuki Nishida, Shigeru Aoki, Ryuichi Noseyama, Kenichiro Ishibashi, Katsunori Nakamura, Nobuo Arai
  • Patent number: 5611316
    Abstract: A fuel supply mechanism for a gas combustion engine has a tank filled with a gas fuel, a fuel injector having a fuel injection valve mounted on the gas combustion engine, a pipe for supplying the gas fuel from the tank to the fuel injector, a gas fuel cutoff valve in the pipe for cutting off the gas fuel flowing through the pipe, a gas fuel state detector for detecting a state of the gas fuel, and a control unit responsive to a detected signal from the gas fuel state detector for controlling the gas fuel cutoff valve and the fuel injection valve.
    Type: Grant
    Filed: December 28, 1994
    Date of Patent: March 18, 1997
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Yoshikazu Oshima, Atsushi Kato, Mitsuru Ikeo, Toshiyuki Nishida, Kazuhiro Ueda, Katsunori Nakamura, Ryuichi Noseyama, Kenichiro Ishibashi, Shigeru Aoki