Patents by Inventor Katsunori Nishii

Katsunori Nishii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7585706
    Abstract: The semiconductor device of this invention includes an active region formed from a group III nitride semiconductor grown on a substrate and an insulating oxide film formed in a peripheral portion of the active region by oxidizing the group III nitride semiconductor. On the active region, a gate electrode in Schottky contact with the active region extending onto the insulating oxide film and having an extended portion on the insulating oxide film is formed, and ohmic electrodes respectively serving as a source electrode and a drain electrode are formed with space from side edges along the gate length direction of the gate electrode.
    Type: Grant
    Filed: September 18, 2007
    Date of Patent: September 8, 2009
    Assignee: Panasonic Corporation
    Inventors: Katsunori Nishii, Kaoru Inoue, Toshinobu Matsuno, Yoshito Ikeda, Hiroyuki Masato
  • Patent number: 7449399
    Abstract: A semiconductor device has an active region composed of a group III-V nitride semiconductor and ohmic electrodes and a gate electrode each formed on the active region. The active region has an entire surface thereof exposed to a plasma such that a surface potential for electrons therein is lower than in the case where the entire surface is not exposed to the plasma.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: November 11, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kaoru Inoue, Yoshito Ikeda, Yutaka Hirose, Katsunori Nishii
  • Publication number: 20080038856
    Abstract: The semiconductor device of this invention includes an active region formed from a group III nitride semiconductor grown on a substrate and an insulating oxide film formed in a peripheral portion of the active region by oxidizing the group III nitride semiconductor. On the active region, a gate electrode in Schottky contact with the active region extending onto the insulating oxide film and having an extended portion on the insulating oxide film is formed, and ohmic electrodes respectively serving as a source electrode and a drain electrode are formed with space from side edges along the gate length direction of the gate electrode.
    Type: Application
    Filed: September 18, 2007
    Publication date: February 14, 2008
    Applicant: Matsushita Electronics Corporation
    Inventors: Katsunori NISHII, Kaoru INOUE, Toshinobu MATSUNO, Yoshito IKEDA, Hiroyuki MASATO
  • Patent number: 7307292
    Abstract: An insulating-gate semiconductor device has a first nitride semiconductor layer formed over a substrate and an insulating oxidation layer obtained by oxidizing a second nitride semiconductor layer formed on the first nitride semiconductor layer. A gate electrode is formed on the insulating oxidation layer.
    Type: Grant
    Filed: June 9, 2003
    Date of Patent: December 11, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Katsunori Nishii, Kaoru Inoue, Toshinobu Matsuno, Yoshito Ikeda, Hiroyuki Masato
  • Publication number: 20070194295
    Abstract: An active region formed of a Group III nitride semiconductor is formed on a substrate. Then, an electrode is formed on the active region and a protective insulating film is formed on a part of the active region located in the peripheral portion of the electrode by oxidizing the Group III nitride semiconductor.
    Type: Application
    Filed: April 20, 2007
    Publication date: August 23, 2007
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Katsunori Nishii, Yoshito Ikeda, Kaoru Inoue
  • Publication number: 20070020896
    Abstract: A semiconductor device has an active region composed of a group III-V nitride semiconductor and ohmic electrodes and a gate electrode each formed on the active region. The active region has an entire surface thereof exposed to a plasma such that a surface potential for electrons therein is lower than in the case where the entire surface is not exposed to the plasma.
    Type: Application
    Filed: September 27, 2006
    Publication date: January 25, 2007
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kaoru Inoue, Yoshito Ikeda, Yutaka Hirose, Katsunori Nishii
  • Patent number: 7122451
    Abstract: A semiconductor device has an active region composed of a group III–V nitride semiconductor and ohmic electrodes and a gate electrode each formed on the active region. The active region has an entire surface thereof exposed to a plasma such that a surface potential for electrons therein is lower than in the case where the entire surface is not exposed to the plasma.
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: October 17, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kaoru Inoue, Yoshito Ikeda, Yutaka Hirose, Katsunori Nishii
  • Patent number: 7105907
    Abstract: A buffer layer, an undoped gallium nitride layer, and an n-type gallium nitride active layer are formed on a sapphire substrate. Ohmic contacts and a Schottky contact are then formed on the n-type gallium nitride active layer as a source contact, a drain contact and a gate contact, respectively. The Schottky contact is a copper alloy, such as palladium copper, in which the content by weight of copper is 5%.
    Type: Grant
    Filed: June 3, 2003
    Date of Patent: September 12, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshito Ikeda, Kaoru Inoue, Yutaka Hirose, Katsunori Nishii
  • Patent number: 7037817
    Abstract: A semiconductor device has a first semiconductor layer composed of a group III–V nitride, an oxide film formed by oxidizing a second semiconductor layer composed of a group III–V nitride to be located on the gate electrode formation region of the first semiconductor layer, an insulating film formed on the oxide film to have a composition different from the composition of the oxide film, and a gate electrode formed on the insulating film.
    Type: Grant
    Filed: July 13, 2004
    Date of Patent: May 2, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kaoru Inoue, Yoshito Ikeda, Yutaka Hirose, Katsunori Nishii
  • Patent number: 6933181
    Abstract: In a method for fabricating a semiconductor device, a first semiconductor layer of aluminum gallium nitride is first formed on a substrate, and a protection film containing silicon is then formed on the first semiconductor layer in such a manner that a device-isolation region is uncovered. Thereafter, the method further includes the step of heat-treating the first semiconductor layer in an oxidizing atmosphere whose temperature is adjusted to be within a range of 950° C. or more and 1050° C. or less.
    Type: Grant
    Filed: July 17, 2003
    Date of Patent: August 23, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kaoru Inoue, Yoshito Ikeda, Katsunori Nishii, Yutaka Hirose
  • Patent number: 6924516
    Abstract: A semiconductor device includes: a substrate; a buffer layer including GaN formed on the substrate, wherein: surfaces of the buffer layer are c facets of Ga atoms; a channel layer including GaN or InGaN formed on the buffer layer,wherein: surfaces of the channel layer are c facets of Ga or In atoms; an electron donor layer including AlGaN formed on the channel layer, wherein: surfaces of the electron donor layer are c facets of Al or Ga atoms; a source electrode and a drain electrode formed on the electron donor layer; a cap layer including GaN or InGaAlN formed between the source electrode and the drain electrode, wherein: surfaces of the cap layer are c facets of Ga or In atoms and at least a portion of the cap layer is in contact with the electron donor layer; and a gate electrode formed at least a portion of which is in contact with the cap layer.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: August 2, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kaoru Inoue, Katsunori Nishii, Hiroyuki Masato
  • Patent number: 6852612
    Abstract: The semiconductor device of the present invention includes: a gallium nitride (GaN) compound semiconductor layer; and a Schottky electrode formed on the GaN compound semiconductor layer, wherein the Schottky electrode contains silicon.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: February 8, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Katsunori Nishii, Yoshito Ikeda, Hiroyuki Masato, Kaoru Inoue
  • Publication number: 20050001234
    Abstract: A semiconductor device includes: a substrate; a buffer layer including GaN formed on the substrate, wherein: surfaces of the buffer layer are c facets of Ga atoms; a channel layer including GaN or InGaN formed on the buffer layer, wherein: surfaces of the channel layer are c facets of Ga or In atoms; an electron donor layer including AlGaN formed on the channel layer, wherein: surfaces of the electron donor layer are c facets of Al or Ga atoms; a source electrode and a drain electrode formed on the electron donor layer; a cap layer including GaN or InGaAlN formed between the source electrode and the drain electrode, wherein: surfaces of the cap layer are c facets of Ga or In atoms and at least a portion of the cap layer is in contact with the electron donor layer; and a gate electrode formed at least a portion of which is in contact with the cap layer.
    Type: Application
    Filed: August 26, 2004
    Publication date: January 6, 2005
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Kaoru INOUE, Katsunori NISHII, Hiroyuki MASATO
  • Publication number: 20040238860
    Abstract: A semiconductor device has a first semiconductor layer composed of a group III-V nitride, an oxide film formed by oxidizing a second semiconductor layer composed of a group III-V nitride to be located on the gate electrode formation region of the first semiconductor layer, an insulating film formed on the oxide film to have a composition different from the composition of the oxide film, and a gate electrode formed on the insulating film.
    Type: Application
    Filed: July 13, 2004
    Publication date: December 2, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO.,LTD.
    Inventors: Kaoru Inoue, Yoshito Ikeda, Yutaka Hirose, Katsunori Nishii
  • Patent number: 6812505
    Abstract: A semiconductor device includes: a substrate; a buffer layer including GaN formed on the substrate, wherein: surfaces of the buffer layer are c facets of Ga atoms; a channel layer including GaN or InGaN formed on the buffer layer, wherein: surfaces of the channel layer are c facets of Ga or In atoms; an electron donor layer including AlGaN formed on the channel layer, wherein: surfaces of the electron donor layer are c facets of Al or Ga atoms; a source electrode and a drain electrode formed on the electron donor layer; a cap layer including GaN or InGaAlN formed between the source electrode and the drain electrode, wherein: surfaces of the cap layer are c facets of Ga or In atoms and at least a portion of the cap layer is in contact with the electron donor layer; and a gate electrode formed at least a portion of which is in contact with the cap layer.
    Type: Grant
    Filed: September 2, 2003
    Date of Patent: November 2, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kaoru Inoue, Katsunori Nishii, Hiroyuki Masato
  • Patent number: 6809352
    Abstract: The semiconductor device of the present invention includes: a gallium nitride (GaN) compound semiconductor layer; and a Schottky electrode formed on the GaN compound semiconductor layer, wherein the Schottky electrode contains silicon.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: October 26, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Katsunori Nishii, Yoshito Ikeda, Hiroyuki Masato, Kaoru Inoue
  • Publication number: 20040175853
    Abstract: A semiconductor device has an active region composed of a group III-V nitride semiconductor and ohmic electrodes and a gate electrode each formed on the active region. The active region has an entire surface thereof exposed to a plasma such that a surface potential for electrons therein is lower than in the case where the entire surface is not exposed to the plasma.
    Type: Application
    Filed: February 26, 2004
    Publication date: September 9, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Kaoru Inoue, Yoshito Ikeda, Yutaka Hirose, Katsunori Nishii
  • Patent number: 6774449
    Abstract: The semiconductor device of the present invention includes: a gallium nitride (GaN) compound semiconductor layer; and a Schottky electrode formed on the GaN compound semiconductor layer, wherein the Schottky electrode contains silicon.
    Type: Grant
    Filed: September 18, 2000
    Date of Patent: August 10, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Katsunori Nishii, Yoshito Ikeda, Hiroyuki Masato, Kaoru Inoue
  • Patent number: 6770922
    Abstract: A semiconductor device has a first semiconductor layer composed of a group III-V nitride, an oxide film formed by oxidizing a second semiconductor layer composed of a group III-V nitride to be located on the gate electrode formation region of the first semiconductor layer, an insulating film formed on the oxide film to have a composition different from the composition of the oxide film, and a gate electrode formed on the insulating film.
    Type: Grant
    Filed: February 26, 2003
    Date of Patent: August 3, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kaoru Inoue, Yoshito Ikeda, Yutaka Hirose, Katsunori Nishii
  • Publication number: 20040137761
    Abstract: In a method for fabricating a semiconductor device, a first semiconductor layer of aluminum gallium nitride is first formed on a substrate, and a protection film containing silicon is then formed on the first semiconductor layer in such a manner that a device-isolation region is uncovered. Thereafter, the method further includes the step of heat-treating the first semiconductor layer in an oxidizing atmosphere whose temperature is adjusted to be within a range of 950° C. or more and 1050 ° C. or less.
    Type: Application
    Filed: July 17, 2003
    Publication date: July 15, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Kaoru Inoue, Yoshito Ikeda, Katsunori Nishii, Yutaka Hirose