Patents by Inventor Katsunori Ueno

Katsunori Ueno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170170258
    Abstract: In order to improve the dynamic characteristics of a vertical MOSFET using GaN, it is an objective of the present invention to reduce the resistance of a current path with a long hole movement distance in a p-type well. Provided is a vertical MOSFET including a gallium nitride layer having a main surface that is a non-polar surface; a p-type well region that is provided with a stripe shape in the main surface of the gallium nitride layer; and a stripe-shaped electrode provided above the p-type well region. Hole mobility is higher in a direction orthogonal to an extension direction of the stripe-shaped electrode than in the extension direction, among directions in a plane parallel to the main surface.
    Type: Application
    Filed: October 27, 2016
    Publication date: June 15, 2017
    Inventors: Shinya TAKASHIMA, Katsunori UENO, Masaharu EDO
  • Publication number: 20170092758
    Abstract: To more easily form a structure that mitigates the electrical field focus at the bottom portion of the trench gate and prevents decreases and variations in the gate threshold value (Vth), provided is a semiconductor device including a semiconductor substrate; a second semiconductor region with a second conduction type that is provided above the semiconductor substrate and includes a first semiconductor region with a first conduction type in a portion thereof; a third semiconductor region that is provided above the second semiconductor region and has a higher second conduction type impurity concentration than the second semiconductor region; and a gate trench that penetrates through the third semiconductor region and is provided on top of the first semiconductor region. The gate trench includes a gate insulating film provided on side walls and a bottom portion of the gate trench and a gate electrode provided in contact with the gate insulating film.
    Type: Application
    Filed: July 26, 2016
    Publication date: March 30, 2017
    Inventor: Katsunori UENO
  • Publication number: 20170062220
    Abstract: A method of manufacturing a nitride semiconductor device is provided, comprising: forming, on a substrate, a first laminated body where a first nitride semiconductor layer, a second nitride semiconductor layer and a third nitride semiconductor layer are laminated in this order; subsequent to the forming, removing a partial region of the third nitride semiconductor layer, subsequent to the removing; implanting ions to the first nitride semiconductor layer from the partial region where the third nitride semiconductor layer is removed at least through the second nitride semiconductor layer; and subsequent to the implanting the ions, annealing the first laminated body.
    Type: Application
    Filed: June 29, 2016
    Publication date: March 2, 2017
    Inventors: Ryo TANAKA, Shinya TAKASHIMA, Katsunori UENO, Masaharu EDO
  • Publication number: 20170062084
    Abstract: An object of the invention is to provide a reactor instrumentation system that can be easily repaired or replaced. The invention includes: an instrumentation tube provided in a reactor core; a gas flow pipe provided in the instrumentation tube; a suction mechanism for supplying gas containing oxygen to the gas flow pipe; and a nuclide analysis device for measuring a nuclide in the gas in the gas flow pipe. According to the invention, it is possible to provide a reactor instrumentation system that can be easily repaired or replaced.
    Type: Application
    Filed: May 13, 2016
    Publication date: March 2, 2017
    Inventors: Kouichi OKADA, Takahiro TADOKORO, Katsunori UENO, Yasushi NAGUMO
  • Publication number: 20160365438
    Abstract: The region having the surface roughness has nitrogen vacancies, which serve as compensating donors for acceptors and therefore cannot achieve a sufficiently high p-type carrier concentration. In addition, the surface of the GaN-based material may be contaminated as a result of diffusion of impurities from the protective film or insufficient removal of the protective film. Such contamination may adversely affect the subsequent steps or the characteristics of completed devices. A first aspect of the innovations herein provides a method of manufacturing a nitride semiconductor device, including thermally treating a nitride semiconductor layer or removing a film formed on a front surface of the nitride semiconductor layer, and polishing the front surface of the nitride semiconductor layer after the thermally treating or the removing.
    Type: Application
    Filed: March 3, 2016
    Publication date: December 15, 2016
    Inventors: Shinya TAKASHIMA, Ryo TANAKA, Katsunori UENO, Masaharu EDO
  • Publication number: 20160363504
    Abstract: A radioactive gas measurement apparatus comprises: a radiation measurement cell comprising an inlet pipe and a discharge pipe, the radiation measurement cell introducing and discharging a radioactive gas containing a nuclide to be measured and a positron emitter nuclide through the inlet pipe and the discharge pipe; a radiation detector for measuring a radiation generated from the radioactive gas; and a radiation collimator allowing the radiation measurement cell to communicate with the radiation detector and setting a predetermined radiation measurement geometry condition between the radiation measurement cell and the radiation detector. Then, as the predetermined radiation measurement geometry condition, an inner wall area of the radiation measurement cell which the radiation detector views through the radiation collimator is set equal to or less than a half of a total inner wall area of the radiation measurement cell.
    Type: Application
    Filed: September 21, 2010
    Publication date: December 15, 2016
    Inventors: Hiroshi KITAGUCHI, Takahiro Tadokoro, Katsunori Ueno, Hitoshi Kuwabara
  • Patent number: 9519067
    Abstract: A radioactive gas measurement apparatus comprises: a radiation measurement cell comprising an inlet pipe and a discharge pipe, the radiation measurement cell introducing and discharging a radioactive gas containing a nuclide to be measured and a positron emitter nuclide through the inlet pipe and the discharge pipe; a radiation detector for measuring a radiation generated from the radioactive gas; and a radiation collimator allowing the radiation measurement cell to communicate with the radiation detector and setting a predetermined radiation measurement geometry condition between the radiation measurement cell and the radiation detector. Then, as the predetermined radiation measurement geometry condition, an inner wall area of the radiation measurement cell which the radiation detector views through the radiation collimator is set equal to or less than a half of a total inner wall area of the radiation measurement cell.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: December 13, 2016
    Assignee: HITACHI, LTD.
    Inventors: Hiroshi Kitaguchi, Takahiro Tadokoro, Katsunori Ueno, Hitoshi Kuwabara
  • Patent number: 9478645
    Abstract: Provided is a longitudinal bidirectional device in which current flows in a layering direction of a semiconductor layered portion formed on a front surface of a substrate, the bidirectional device comprising a first semiconductor element that includes a first channel and is formed on the semiconductor layered portion; and a second semiconductor element that includes a second channel and is provided on the substrate side of the first semiconductor element within the semiconductor layered portion. The first semiconductor element further includes a first control electrode that controls the first channel and that is formed on a surface of the semiconductor layered portion that faces away from the substrate, and the second semiconductor element is formed on at least a portion of the surface of the semiconductor layered portion on which the first control electrode is formed and includes a second control electrode that controls the second channel.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: October 25, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Katsunori Ueno
  • Patent number: 9450084
    Abstract: A semiconductor device having high reliability and high load short circuit withstand capability while maintaining a low ON resistance is provided, by using a WBG semiconductor as a switching element of an inverter circuit. In the semiconductor device for application to a switching element of an inverter circuit, a band gap of a semiconductor material is wider than that of silicon, a circuit that limits a current when a main transistor is short circuited is provided, and the main transistor that mainly serves to pass a current, a sensing transistor that is connected in parallel to the main transistor and detects a microcurrent proportional to a current flowing in the main transistor, and a lateral MOSFET that controls a gate of the main transistor on the basis of an output of the sensing transistor are formed on the same semiconductor.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: September 20, 2016
    Assignee: FUJI ELECTRIC SYSTEMS CO. LTD.
    Inventor: Katsunori Ueno
  • Patent number: 9431391
    Abstract: A semiconductor device having high breakdown withstand voltage includes a first element which is a normally-on type transistor made of nitride compound semiconductor, a second element which is connected to the first element in series and is a transistor having withstand voltage between a source and a drain lower than withstand voltage of the first element, a first diode which is connected between a gate of the first element or a gate of the second element and a drain of the first element so that a cathode of the first diode is connected at the drain's side and has predetermined avalanche withstand voltage, and a first resistance connected to the gate to which the first diode is connected. The avalanche withstand voltage of the first diode is lower than breakdown voltage of the first element.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: August 30, 2016
    Assignees: Furukawa Electric Co., Ltd., Fuji Electric Co., Ltd.
    Inventor: Katsunori Ueno
  • Patent number: 9274233
    Abstract: Provided is a measurement unit and measurement method for reducing attenuation due to optical fiber length and SN degradation due to background in a dosage rate monitor that uses optical fiber. This system comprises: a radiation detector for detecting radiation dosage; a light source for irradiating stimulating light on the radiation detector; a photodetector for detecting light generated by the radiation detector; an optical fiber for connecting the photodetector and the radiation detector and light source, and transmitting light from the light source and light from the radiation detector; a measurement unit for counting the pulses outputted from the photodetector; and an analysis unit for extracting the luminous energy originating from the radiation detector, from time information, wave height information, and the count value, which are measurement results obtained by the measurement unit, and converting the luminous energy to a dosage and dosage rate.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: March 1, 2016
    Assignee: Hitachi, Ltd.
    Inventors: Katsunori Ueno, Hiroshi Kitaguchi, Takahiro Tadokoro, Akihisa Kaihara, Koichi Okada, Yoshinobu Sakakibara, Yuta Inamura, Hitoshi Kuwabara
  • Publication number: 20150380498
    Abstract: A method for producing a semiconductor device having a nitride-based semiconductor layer includes forming a first nitride-based semiconductor layer of AlxGa1-xN on a base; forming a second nitride-based semiconductor layer of AlyGa1-yN on the first nitride-based semiconductor layer; forming a third nitride-based semiconductor layer of AlzGa1-zN on the second nitride-based semiconductor layer; introducing an impurity using ion implantation into the first, second, and third nitride-based semiconductor layers; and thermally treating, after ion implantation, the first, second, and third nitride-based semiconductor layers, wherein the first, second, and third nitride-based semiconductor layers have respective Al composition ratios x, y, and z, and the Al composition ratio y of the second nitride-based semiconductor layer is higher than the Al composition ratio x of the first nitride-based semiconductor layer, and higher than the Al composition ratio z of the third nitride-based semiconductor layer.
    Type: Application
    Filed: September 9, 2015
    Publication date: December 31, 2015
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Ryo TANAKA, Shinya TAKASHIMA, Katsunori UENO, Masaharu EDO
  • Publication number: 20150380238
    Abstract: A method for producing a semiconductor device having a nitride-based semiconductor layer includes forming an aluminum nitride layer on a surface of the nitride-based semiconductor layer at a forming temperature and in a growth atmosphere for aluminum nitride; and performing a thermal treatment on the nitride-based semiconductor layer and the aluminum nitride layer, at a treatment temperature that is higher than the forming temperature and in the growth atmosphere for aluminum nitride. For example, an n-GaN layer is formed on an n-GaN substrate, and thereafter the n-GaN layer is doped with an impurity. A cap layer of an epitaxial film made up of AlN is formed, by MOCVD, on the surface of the n-GaN layer. Thermal treatment for activation annealing activates the impurity in the n-GaN layer in an atmosphere that causes AlN to grow, or in an atmosphere in which growth and decomposition of AlN are substantially balanced.
    Type: Application
    Filed: September 8, 2015
    Publication date: December 31, 2015
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Shinya TAKASHIMA, Ryo TANAKA, Katsunori UENO, Masaharu EDO
  • Publication number: 20150123002
    Abstract: Provided is a measurement unit and measurement method for reducing attenuation due to optical fiber length and SN degradation due to background in a dosage rate monitor that uses optical fiber. This system comprises: a radiation detector for detecting radiation dosage; a light source for irradiating stimulating light on the radiation detector; a photodetector for detecting light generated by the radiation detector; an optical fiber for connecting the photodetector and the radiation detector and light source, and transmitting light from the light source and light from the radiation detector; a measurement unit for counting the pulses outputted from the photodetector; and an analysis unit for extracting the luminous energy originating from the radiation detector, from time information, wave height information, and the count value, which are measurement results obtained by the measurement unit, and converting the luminous energy to a dosage and dosage rate.
    Type: Application
    Filed: December 3, 2012
    Publication date: May 7, 2015
    Applicant: HITACHI, LTD.
    Inventors: Katsunori Ueno, Hiroshi Kitaguchi, Takahiro Tadokoro, Akihisa Kaihara, Koichi Okada, Yoshinobu Sakakibara, Yuta Inamura, Hitoshi Kuwabara
  • Patent number: 8928003
    Abstract: The present invention prevents breakage of a gate insulating film of a MOS device and provides a nitride semiconductor device having improved reliability. An SBD metal electrode provided between a drain electrode and a gate electrode is configured to form a Schottky junction with an AlGaN layer. Further, the SBD metal electrode and a source electrode are connected and electrically short-circuited. Consequently, when an off signal is inputted to the gate electrode, a MOSFET part is turned off and the drain-side voltage of the MOSFET part becomes close to the drain electrode voltage. When the drain electrode voltage increases, the SBD metal electrode voltage becomes lower than the drain-side voltage of the MOSFET part, thus the drain side of the MOSFET part and the drain electrode are electrically disconnected by the SBD metal electrode.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: January 6, 2015
    Assignees: Furukawa Electric Co., Ltd., Fuji Electric Co., Ltd.
    Inventors: Katsunori Ueno, Shusuke Kaya
  • Publication number: 20140346570
    Abstract: A semiconductor device having high breakdown withstand voltage includes a first element which is a normally-on type transistor made of nitride compound semiconductor, a second element which is connected to the first element in series and is a transistor having withstand voltage between a source and a drain lower than withstand voltage of the first element, a first diode which is connected between a gate of the first element or a gate of the second element and a drain of the first element so that a cathode of the first diode is connected at the drain's side and has predetermined avalanche withstand voltage, and a first resistance connected to the gate to which the first diode is connected. The avalanche withstand voltage of the first diode is lower than breakdown voltage of the first element.
    Type: Application
    Filed: September 11, 2013
    Publication date: November 27, 2014
    Applicant: Advanced Power Device Research Association
    Inventor: Katsunori UENO
  • Publication number: 20140345583
    Abstract: A semiconductor device includes an IGBT, a constant voltage circuit, and protection Zener diodes. The IGBT makes/breaks a low-voltage current flowing in a primary coil. The constant voltage circuit and the protection Zener diodes are provided between an external gate terminal and an external collector terminal. The constant voltage circuit supplies a constant gate voltage to the IGBT to thereby set a saturation current value of the IGBT to a predetermined limiting current value. The IGBT has the saturation current value in a limiting current value range of the semiconductor device.
    Type: Application
    Filed: August 7, 2014
    Publication date: November 27, 2014
    Inventor: Katsunori UENO
  • Patent number: 8842797
    Abstract: A gamma scanning apparatus includes a moving and fixing mechanism which moves/fixes a housing to a definite position, and a rotating and moving mechanism which moves a fuel assembly vertically in addition to rotating the assembly. A gamma-ray counting circuit measures an output of a gamma-ray detector, and a data collecting/analyzing and controlling apparatus analyzes data output from the gamma-ray counting circuit, in association with data relating to the rotation and movement of the fuel assembly by the rotating and moving mechanism. The rotating and moving mechanism, after fixing the vertical position of the fuel assembly with the housing also fixed, rotates the fuel assembly through 360° with its height kept constant, and during the 360° rotation of the fuel assembly, the gamma-ray counting circuit measures either a time average of count values of the detector during the rotation or an integral value within a fixed time.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: September 23, 2014
    Assignee: Hitachi-GE Nuclear Energy, Ltd.
    Inventors: Takahiro Tadokoro, Hiroshi Kitaguchi, Katsunori Ueno, Yutaka Iwata, Ryusuke Kimura
  • Patent number: 8836042
    Abstract: A semiconductor device includes an IGBT, a constant voltage circuit, and protection Zener diodes. The IGBT makes/breaks a low-voltage current flowing in a primary coil. The constant voltage circuit and the protection Zener diodes are provided between an external gate terminal and an external collector terminal. The constant voltage circuit supplies a constant gate voltage to the IGBT to thereby set a saturation current value of the IGBT to a predetermined limiting current value. The IGBT has the saturation current value in a limiting current value range of the semiconductor device.
    Type: Grant
    Filed: August 11, 2009
    Date of Patent: September 16, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Katsunori Ueno
  • Patent number: 8829568
    Abstract: An insulating layer, an undoped first GaN layer and an AlGaN layer are laminated in this order on a surface of a semiconductor substrate. A surface barrier layer formed by a two-dimensional electron gas is provided in an interface between the first GaN layer and the AlGaN layer. A recess (first recess) which reaches the first GaN layer but does not pierce the first GaN layer is formed in a surface layer of the AlGaN layer. A first high withstand voltage transistor and a control circuit are formed integrally on the aforementioned semiconductor substrate. The first high withstand voltage transistor is formed in the first recess and on a surface of the AlGaN layer. The control circuit includes an n-channel MOSFET formed in part of the first recess, and a depression type n-channel MOSFET formed on a surface of the AlGaN layer.
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: September 9, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Katsunori Ueno