Abstract: A parallel storage allocation method and device in which each space in a memory section that is available for use is associated with a respective allocator and stores an identifier for the respective allocator, data identifying allocators not in use is stored, and a list of allocators associated with spaces which are available for use is maintained. Each time a memory space is no longer in use a check is made to determine the allocator identifier of any already free space which can be combined with the memory space that is no longer in use. A liberate space token is generated which includes a first identifier corresponding to an allocator which is not in use and a second identifier which corresponds to any already free space to be combined. If the list of allocators relative to available space does not contain the allocator having the second identifier, the allocator having the first identifier is entered in the list with details of the no longer in use space.

Abstract: A delay management method and device in which, when a data read request is made relating to data which has not yet reached a memory section, that read request is delayed and sent to a delay management section. The read request data is sent to a free address in the delay management section selected from a store of free addresses in the memory section. The delay management section stores the read request data at the free address. The delay management section communicates free addresses to the memory section.

Abstract: An image processing apparatus includes a memory having a first region and a second region. The first memory region holds original image data. A first calculation device calculates addresses of segments of the first memory region. A second calculation device calculates addresses of segments of the second memory region. The original image data are transferred from the first memory region to the second memory region in accordance with the calculated addresses of the segments of the first and second memory regions. The first calculation device and the second calculation device are mutually independent. The calculation of the addresses of the segments of the first memory region is performed simultaneously with the calculation of the addresses of the segments of the second memory region.

Abstract: A data packet shortening method for shortening data packets passed between first and second devices. The data packets include address data which is sent from the first device to the second device and returned to the first device unchanged. The address data is temporarily stored at an address of a memory device, and the address data and the address of that data in the memory device is sent from the first device to the second device. When it is necessary to communicate the address data from the second device to the first device a data packet is sent which includes the address of that data in the memory device but does not include the actual address data. The required address data is derived by the first device from the address of that data in the memory device.

Abstract: An apparatus for expanding or contracting image data includes an input for storing the image data to be processed, a first barrel shifter for shifting the output data of the input register, a control register for storing a mapping pattern which indicates a position of the image data bits to be extracted in the expansion mode or which indicates the number of times when the image data are to be copied, an expansion and contraction circuit for expanding or contracting the image data by referring to the mapping pattern, and a second barrel register for shifting the output image data of the expansion and contraction circuit before the data are loaded in an output data register.

Abstract: Image data is transposed between successively arranged first data points in a first image field and successively arranged second data points in a second image field by a method comprising: (1) successively specifying a first data point (i); (2) summing first control data indicative of a residue with second control data indicative of a constant value; (3.sub.1) if the result of the summation does not exceed a predetermined value, updating the first control data with the summation result and specifying a second data point (j) corresponding to the specified first data point, or (3.sub.

Abstract: A plurality of registers included in a central processing unit are electrically divided into a plurality of register-sets which are arranged in a given order to be used as a stack where one of the register-sets at the top of stack is normally used for executing the program of a main routine. In one embodiment, the data of the register-sets are pushed down for executing interrupt service routines and then popped up for resuming the suspended program. When all of the register-sets are loaded, the data may be saved in a saving region of a main memory, and the saved data may be directly transferred to the top register-set when needed. In another embodiment, actual push down and popping up of data are not performed but one of the register-sets is selectively enabled so that the register-sets function as a stack.