Patents by Inventor Katsushi Akita

Katsushi Akita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10822722
    Abstract: In a gallium arsenide crystal body, an etching pit density of the gallium arsenide crystal body is more than or equal to 10 cm?2 and less than or equal to 10000 cm?2, and an oxygen concentration of the gallium arsenide crystal body is less than 7.0×1015 atoms·cm?3. In a gallium arsenide crystal substrate, an etching pit density of the gallium arsenide crystal substrate is more than or equal to 10 cm?2 and less than or equal to 10000 cm?2, and an oxygen concentration of the gallium arsenide crystal substrate is less than 7.0×1015 atoms·cm?3.
    Type: Grant
    Filed: July 4, 2017
    Date of Patent: November 3, 2020
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hiroshi Fukunaga, Katsushi Akita, Yukio Ishikawa
  • Patent number: 10714640
    Abstract: A semiconductor stacked body includes: a first semiconductor layer containing a group III-V compound semiconductor and being a layer whose conductivity type is a first conductivity type; a quantum-well light-receiving layer containing a group III-V compound semiconductor; a second semiconductor layer containing a group III-V compound semiconductor; and a third semiconductor layer containing a group III-V compound semiconductor and being a layer whose conductivity type is a second conductivity type. The first semiconductor layer, the quantum-well light-receiving layer, the second semiconductor layer, and the third semiconductor layer are stacked in this order. The concentration of an impurity that generates a carrier of the second conductivity type is 1×1014 cm?3 or more and 1×1017 cm?3 or less in the second semiconductor layer.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: July 14, 2020
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takuma Fuyuki, Suguru Arikata, Susumu Yoshimoto, Katsushi Akita
  • Publication number: 20190264348
    Abstract: In a gallium arsenide crystal body, an etching pit density of the gallium arsenide crystal body is more than or equal to 10 cm?2 and less than or equal to 10000 cm?2, and an oxygen concentration of the gallium arsenide crystal body is less than 7.0×1015 atoms·cm?3. In a gallium arsenide crystal substrate, an etching pit density of the gallium arsenide crystal substrate is more than or equal to 10 cm?2 and less than or equal to 10000 cm?2, and an oxygen concentration of the gallium arsenide crystal substrate is less than 7.0×1015 atoms·cm?3.
    Type: Application
    Filed: July 4, 2017
    Publication date: August 29, 2019
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Hiroshi FUKUNAGA, Katsushi AKITA, Yukio ISHIKAWA
  • Patent number: 10326034
    Abstract: A semiconductor layer includes a first semiconductor layer containing a III-V group compound semiconductor and having a first conductivity type, a quantum-well structure containing a III-V group compound semiconductor, a second semiconductor layer containing a III-V group compound semiconductor, a third semiconductor layer containing a III-V group compound semiconductor, and a fourth semiconductor layer containing a III-V group compound semiconductor and having a second conductivity type different from the first conductivity type. The first semiconductor layer, the quantum-well structure, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are stacked in this order. The concentration of an impurity that generates carriers of the second conductivity type is lower in the third semiconductor layer than in the fourth semiconductor layer.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: June 18, 2019
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Suguru Arikata, Takuma Fuyuki, Susumu Yoshimoto, Takashi Kyono, Katsushi Akita
  • Publication number: 20190044010
    Abstract: A semiconductor layer includes a first semiconductor layer containing a III-V group compound semiconductor and having a first conductivity type, a quantum-well structure containing a III-V group compound semiconductor, a second semiconductor layer containing a III-V group compound semiconductor, a third semiconductor layer containing a III-V group compound semiconductor, and a fourth semiconductor layer containing a III-V group compound semiconductor and having a second conductivity type different from the first conductivity type. The first semiconductor layer, the quantum-well structure, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are stacked in this order. The concentration of an impurity that generates carriers of the second conductivity type is lower in the third semiconductor layer than in the fourth semiconductor layer.
    Type: Application
    Filed: January 24, 2017
    Publication date: February 7, 2019
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Suguru ARIKATA, Takuma FUYUKI, Susumu YOSHIMOTO, Takashi KYONO, Katsushi AKITA
  • Publication number: 20190035954
    Abstract: A semiconductor stacked body includes: a first semiconductor layer containing a group III-V compound semiconductor and being a layer whose conductivity type is a first conductivity type; a quantum-well light-receiving layer containing a group III-V compound semiconductor; a second semiconductor layer containing a group III-V compound semiconductor; and a third semiconductor layer containing a group III-V compound semiconductor and being a layer whose conductivity type is a second conductivity type. The first semiconductor layer, the quantum-well light-receiving layer, the second semiconductor layer, and the third semiconductor layer are stacked in this order. The concentration of an impurity that generates a carrier of the second conductivity type is 1×1014 cm?3 or more and 1×1017 cm?3 or less in the second semiconductor layer.
    Type: Application
    Filed: January 24, 2017
    Publication date: January 31, 2019
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takuma FUYUKI, Suguru ARIKATA, Susumu YOSHIMOTO, Katsushi AKITA
  • Patent number: 10158035
    Abstract: A semiconductor stack includes a first-conductivity-type layer of a first conductivity type, the first-conductivity-type layer being formed of a III-V compound semiconductor; a quantum well light-receiving layer formed of a III-V compound semiconductor; and a second-conductivity-type layer of a second conductivity type different from the first conductivity type, the second-conductivity-type layer being formed of a III-V compound semiconductor. The first-conductivity-type layer, the quantum well light-receiving layer, and the second-conductivity-type layer are stacked in this order. The quantum well light-receiving layer has a thickness of 0.5 ?m or more. The quantum well light-receiving layer has a carrier concentration of 1×1016 cm?3 or less.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: December 18, 2018
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takuma Fuyuki, Suguru Arikata, Takashi Kyono, Yusuke Yoshizumi, Katsushi Akita
  • Publication number: 20180315890
    Abstract: A semiconductor layered body includes: a plurality of protrusions having first main surfaces along a reference plane and protruding from the reference plane; and a first semiconductor layer disposed at a side of the plurality of protrusions opposite to the first main surfaces so as to connect the plurality of protrusions to one another. Each of the protrusions is composed of a group III nitride that has a dislocation density of less than or equal to 1×108 cm?3, that is expressed by a composition formula of AlxGa1-xN, and that satisfies 0?x<1. The first semiconductor layer is composed of a group III nitride that has a dislocation density of less than or equal to 1×109 cm?3, that is expressed by a composition formula of AlyGa1-yN, and that satisfies 0<y?1.
    Type: Application
    Filed: October 28, 2016
    Publication date: November 1, 2018
    Applicants: Sumitomo Electric Industries, Ltd., RIKEN
    Inventors: Susumu YOSHIMOTO, Masaki UENO, Katsushi AKITA, Yoshiyuki YAMAMOTO, Hideki HIRAYAMA
  • Publication number: 20180122971
    Abstract: A semiconductor stack includes a first-conductivity-type layer of a first conductivity type, the first-conductivity-type layer being formed of a III-V compound semiconductor; a quantum well light-receiving layer formed of a III-V compound semiconductor; and a second-conductivity-type layer of a second conductivity type different from the first conductivity type, the second-conductivity-type layer being formed of a III-V compound semiconductor. The first-conductivity-type layer, the quantum well light-receiving layer, and the second-conductivity-type layer are stacked in this order. The quantum well light-receiving layer has a thickness of 0.5 ?m or more. The quantum well light-receiving layer has a carrier concentration of 1×1016 cm?3 or less.
    Type: Application
    Filed: April 8, 2016
    Publication date: May 3, 2018
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takuma FUYUKI, Suguru ARIKATA, Takashi KYONO, Yusuke YOSHIZUMI, Katsushi AKITA
  • Patent number: 9929301
    Abstract: A semiconductor stack includes a substrate composed of a III-V group compound semiconductor, a buffer layer that is arranged on the substrate and that is composed of a III-V group compound semiconductor, and an active layer that is arranged on the buffer layer and that includes a layer composed of a III-V group compound semiconductor containing Sb as a group V element. A region of the buffer layer including a main surface of the buffer layer adjacent to the substrate includes a high-concentration region having a high total concentration of Si and C compared with another adjacent region.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: March 27, 2018
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takashi Kyono, Suguru Arikata, Katsushi Akita
  • Publication number: 20180062019
    Abstract: A semiconductor stack includes a substrate composed of a III-V group compound semiconductor, a buffer layer that is arranged on the substrate and that is composed of a III-V group compound semiconductor, and an active layer that is arranged on the buffer layer and that includes a layer composed of a III-V group compound semiconductor containing Sb as a group V element. A region of the buffer layer including a main surface of the buffer layer adjacent to the substrate includes a high-concentration region having a high total concentration of Si and C compared with another adjacent region.
    Type: Application
    Filed: January 12, 2016
    Publication date: March 1, 2018
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takashi KYONO, Suguru ARIKATA, Katsushi AKITA
  • Patent number: 9887310
    Abstract: A semiconductor layered structure includes a substrate formed of a III-V compound semiconductor, a buffer layer disposed on and in contact with the substrate and formed of a III-V compound semiconductor, and a quantum well layer disposed on and in contact with the buffer layer and including a plurality of component layers formed of III-V compound semiconductors. The substrate has a diameter of 55 mm or more. At least one of the component layers is formed of a mixed crystal of three or more elements. When the compound semiconductor forming the substrate has a lattice constant d1, the compound semiconductor forming the buffer layer has a lattice constant d2, and the compound semiconductors forming the quantum well layer have an average lattice constant d3, (d2?d1)/d1 is ?3×10?3 or more and 3×10?3 or less, and (d3?d1)/d1 is ?3×10?3 or more and 3×10?3 or less.
    Type: Grant
    Filed: January 19, 2015
    Date of Patent: February 6, 2018
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Katsushi Akita, Kei Fujii, Takashi Kyono, Koji Nishizuka, Kaoru Shibata
  • Publication number: 20170338376
    Abstract: A layered body includes: a plate-like supporting body having a supporting main surface; and a plurality of projection portions disposed on the supporting main surface, each of the plurality of projection portions being composed of a group III nitride and having a dislocation density of not more than 1×108 cm?3. The projection portion preferably has a polygonal planar shape. The projection portion preferably has a plate-like shape. Preferably, each of the plurality of projection portions has a main surface opposite to the supporting body and corresponding to a {0001} plane of the group III nitride of the projection portions, and the adjacent projection portions of the plurality of projection portions have end surfaces facing each other and corresponding to a {11-20} plane of the group III nitride of the projection portions.
    Type: Application
    Filed: October 28, 2016
    Publication date: November 23, 2017
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Susumu YOSHIMOTO, Katsushi AKITA, Masaki UENO, Yoshiyuki YAMAMOTO
  • Patent number: 9818895
    Abstract: Provided are a semiconductor device and an optical sensor device, each having reduced dark current, and detectivity extended toward longer wavelengths in the near-infrared. Further, a method for manufacturing the semiconductor device is provided. The semiconductor device 50 includes an absorption layer 3 of a type II (GaAsSb/InGaAs) MQW structure located on an InP substrate 1, and an InP contact layer 5 located on the MQW structure. In the MQW structure, a composition x (%) of GaAsSb is not smaller than 44%, a thickness z (nm) thereof is not smaller than 3 nm, and z??0.4x+24.6 is satisfied.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: November 14, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kei Fujii, Katsushi Akita, Takashi Ishizuka, Hideaki Nakahata, Yasuhiro Iguchi, Hiroshi Inada, Youichi Nagai
  • Publication number: 20170294547
    Abstract: A semiconductor layered structure includes a base layer, a quantum well structure, and a contact layer. The base layer, the quantum well structure, and the contact layer are disposed so as to be stacked in this order. In the contact layer, a region including a first main surface that is a main surface on a quantum well structure side has a p-type impurity concentration lower than a p-type impurity concentration of a region including a second main surface that is a main surface opposite to the first main surface. A photodiode includes the semiconductor layered structure and an electrode formed on the semiconductor layered structure. A sensor includes the photodiode and a read-out circuit connected to the photodiode.
    Type: Application
    Filed: October 21, 2015
    Publication date: October 12, 2017
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Kaoru SHIBATA, Koji NISHIZUKA, Suguru ARIKATA, Takashi KYONO, Katsushi AKITA
  • Patent number: 9773932
    Abstract: An epitaxial wafer which allows manufacture of a photodiode having suppressed dark current and ensured sensitivity, and a method for manufacturing the epitaxial wafer, are provided. The epitaxial wafer of the present invention includes: a III-V semiconductor substrate; and a multiple quantum well structure disposed on the substrate, and including a plurality of pairs of a first layer and a second layer. The total concentration of elements contained as impurities in the multiple quantum well structure is less than or equal to 5×1015 cm?3.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: September 26, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kei Fujii, Koji Nishizuka, Takashi Kyono, Kaoru Shibata, Katsushi Akita
  • Patent number: 9698287
    Abstract: An epitaxial wafer of the present invention includes a substrate composed of a III-V compound semiconductor, a multiple quantum well structure composed of a III-V compound semiconductor and located on the substrate, and a top layer composed of a III-V compound semiconductor and located on the multiple quantum well structure. The substrate has a plane orientation of (100) and an off angle of ?0.030° or more and +0.030° or less, and a surface of the top layer has a root-mean-square roughness of less than 10 nm.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: July 4, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kei Fujii, Kaoru Shibata, Katsushi Akita
  • Patent number: 9680040
    Abstract: A semiconductor device and the like having high quantum efficiency or high sensitivity in a near-infrared to infrared region is provided. The semiconductor device includes: a substrate; a multiple quantum well structure disposed on the substrate, and including a plurality of pairs of a layer a and a layer b; and a crystal-adjusting layer disposed between the substrate and the multiple quantum well structure. The crystal-adjusting layer includes a first adjusting layer which is made of the same material as the substrate and is in contact with the substrate, and a second adjusting layer which is made of the same material as the layer a or the layer b of the multiple quantum well structure and is in contact with the multiple quantum well structure.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: June 13, 2017
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Kaoru Shibata, Katsushi Akita, Kei Fujii, Takashi Ishizuka
  • Patent number: 9608148
    Abstract: A method for producing a semiconductor element includes a step of forming a multiple quantum well in which a GaSb layer and an InAs layer are alternately stacked on a GaSb substrate by MOVPE, wherein, in the step of forming a multiple quantum well, an InSb film is formed on at least one of a lower-surface side and an upper-surface side of the InAs layer so as to be in contact with the InAs layer.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: March 28, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takashi Kyono, Kei Fujii, Katsushi Akita
  • Publication number: 20170040477
    Abstract: A semiconductor layered structure according to the present invention includes a substrate formed of a III-V compound semiconductor; and semiconductor layers disposed on the substrate and formed of III-V compound semiconductors. The substrate has a majority-carrier-generating impurity concentration of 1×1017 cm?3 or more and 2×1020 cm?3 or less, and the impurity has an activation ratio of 30% or more.
    Type: Application
    Filed: December 17, 2014
    Publication date: February 9, 2017
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Suguru Arikata, Takashi Kyono, Koji Nishizuka, Kaoru Shibata, Katsushi Akita