Abstract: A receiving circuit (100) includes: a channel estimation unit (20) configured to estimate a channel response vector based on a reception signal received via a plurality of antennas (10); a covariance matrix estimation unit (30) configured to estimate a covariance matrix based on the reception signal and the channel response vector; a covariance matrix correction unit (40) configured to correct the covariance matrix by adding, to the covariance matrix, an offset value with a value in components including off-diagonal elements of the matrix; and a weight multiplication unit (50) configured to estimate a transmission signal by multiplying a weight based on the channel response vector and the corrected covariance matrix by the reception signal.

Abstract: A receiving circuit (100) includes: a channel estimation unit (20) configured to estimate a channel response vector based on a reception signal received via a plurality of antennas (10); a covariance matrix estimation unit (30) configured to estimate a covariance matrix based on the reception signal and the channel response vector; a covariance matrix correction unit (40) configured to correct the covariance matrix by adding, to the covariance matrix, an offset value with a value in components including off-diagonal elements of the matrix; and a weight multiplication unit (50) configured to estimate a transmission signal by multiplying a weight based on the channel response vector and the corrected covariance matrix by the reception signal.

Abstract: In one embodiment, an FFT circuit (1) includes a pipeline in which L number of butterfly operational elements each having Single-path Delay Feedback, SDF, architecture are connected with each other. Each of LHF number of butterfly PEs (10), corresponding to a first stage to an LHFth stage, is configured to rearrange output data order such that, in units of N/(2S?1) pieces of output data starting from head output data whose Data Flow Graph, DFG, index i is “0”, intermediate result data GS(i) whose bS(i) is 1 is output after intermediate result data GS(i) whose bS(i) is 0 in the N/(2S?1) pieces of the output data, where N represents the number of FFT points, S represents an integer indicating a stage number, and bS(i) represents the Sth bit from the least significant bit in binary representation of the DFG index i.

Abstract: In an array processing section, using data strings entered from input ports, a plurality of data processor elements execute predetermined operations while transferring data to each other, and output data strings of results of the operations from a plurality of output ports. A first data string converter converts data strings stored in a plurality of data storages of a data storage group into a placement suitable for the operations in the array processing section, and enters the converted data strings into the input ports of the array processing section. A second data string converter converts the data strings output from output ports of the array processing section into a placement to be stored in the plurality of data storages of the data storage group.

Abstract: A processor includes a loop counter that is reset to 0 when a loop instruction for executing a process in a loop from a loop start address to a loop end address is issued, a data memory that receives data that is used for executing a process in the loop, in which the data is transferred from outside, a calculator that uses the data transferred to the data memory to execute the process in the loop, a data counter that increments the loop counter by 1 every time a certain amount of data that is used for executing a process in the loop is transferred from outside to a data memory, and a loop controller that decrements the loop counter by 1 and causes the calculator to execute the process in the loop when a loop count value of the loop counter is not 0.

Abstract: In one embodiment, an FFT circuit (1) includes a pipeline in which L number of butterfly operational elements each having Single-path Delay Feedback, SDF, architecture are connected with each other. Each of LBF number of butterfly PEs (10), corresponding to a first stage to an LHFth stage, is configured to rearrange output data order such that, in units of N/(2S?1) pieces of output data starting from head output data whose Data Flow Graph, DFG, index i is “0”, intermediate result data GS(i) whose bS(i) is 1 is output after intermediate result data GS(i) whose bS(i) is 0 in the N/(2S?1) pieces of the output data, where N represents the number of FFT points, S represents an integer indicating a stage number, and bS(i) represents the Sth bit from the least significant bit in binary representation of the DFG index i.

Abstract: Disclosed is a processor that is able to efficiently execute DFT operations without having part of a basic operational circuit idle even during non-DFT-operation processing. The processor (1) has an operational means (operation unit) (2) and a control means (control unit) (3). The operation means (2) has a plurality of shift addition-and-subtraction means connected such that CORDIC (COordinate Rotation DIgital Computer) operations can be executed. The shift adding-and-subtracting means also execute shift addition-and-subtraction processing of butterfly operations that process shift addition-and-subtraction for one stage or more. The control means (3) instructs the operation means (2) to execute either CORDIC operations or butterfly operations, based on a plurality of data received from the outside.

Abstract: A data rearranging circuit includes variable delay means and control means. The variable delay means, by imparting a delay of a number of delay cycles that differs for each input cycle and moreover for each port to each unit of data of a data group that is applied as input to a plurality of ports and in a plurality of cycles, switches the order of the data in the same port and supplies the data as the data group at a predetermined delay. The control means supplies control information that includes the number of delay cycles used in the variable delay means.

Abstract: A linear systolic array is added to the lower side of a trapezoid systolic array created by combining a triangular systolic array and a square systolic array. In order to make the connection among the cells fixed, the intermediate result output from each row of the trapezoid systolic array to a lower row is shifted in phase with respect to the intermediate result of the complex MFA algorithm, the phase shift is absorbed by the next row, and the phase shift in the intermediate result output from the last row of the trapezoid systolic array is corrected by the linear systolic array. Each cell is implemented by a CORDIC circuit that processes vector angle computation, vector rotation, division, and multiply-and-accumulate with a constant delay.

Abstract: Disclosed is a CORDIC circuit in which scale correction process is divided into two stages: rough correction and fine correction, and a second-process of a pseudo-rotation process is performed in parallel with the fine scale correction. A range of the fine scale correction is set so that it is not necessary to perform a scale correction with regard to a remaining rotation angle of the first half of the pseudo-rotation process.

Abstract: To provide a dynamic image receiving apparatus which receives dynamic image streams coded with inter-frame prediction such as MPEG from a plurality of channels, and collects the dynamic image streams containing intra-frame coded pictures from each channel in a short time. The dynamic image receiving apparatus includes: a time information accumulative processing device which accumulates code receiving time of the intra-frame coded picture of the dynamic image stream, and periodicity time information containing one of or both of presentation time information and decoding time information contained in the dynamic image stream for each dynamic image stream of the plurality of channels; code receiving time predicting devices which predict the code receiving time of the intra-frame coded pictures based on the periodicity time information; and a channel selection control device which controls channel selection of the dynamic image stream to be received based on the predicted code receiving time information.

Abstract: Disclosed is a processor that is able to efficiently execute DFT operations without having part of a basic operational circuit idle even during non-DFT-operation processing. The processor (1) has an operational means (operation unit) (2) and a control means (control unit) (3). The operation means (2) has a plurality of shift addition-and-subtraction means connected such that CORDIC (COordinate Rotation DIgital Computer) operations can be executed. The shift adding-and-subtracting means also execute shift addition-and-subtraction processing of butterfly operations that process shift addition-and-subtraction for one stage or more. The control means (3) instructs the operation means (2) to execute either CORDIC operations or butterfly operations, based on a plurality of data received from the outside.

Abstract: A data rearranging circuit includes variable delay means and control means. The variable delay means, by imparting a delay of a number of delay cycles that differs for each input cycle and moreover for each port to each unit of data of a data group that is applied as input to a plurality of ports and in a plurality of cycles, switches the order of the data in the same port and supplies the data as the data group at a predetermined delay. The control means supplies control information that includes the number of delay cycles used in the variable delay means.

Abstract: The present invention provides a processor comprising: a loop counter that is reset to 0 when a loop instruction for executing a process in a loop from a loop start address to a loop end address is issued; a data memory that receives, from outside, data that is used for executing a process in the loop; a calculator that uses the data transferred to said data memory to execute the process in the loop; a data counter that increments said loop counter by 1 every time a certain amount of data is transferred from outside to said data memory; and a loop controller that decrements said loop counter by 1 and causes said calculator to execute the process in the loop when the loop count value of said loop counter is not 0.

Abstract: Disclosed is a one-dimensional MFA systolic array for matrix computation using an MFA (modified Faddeeva algorithm), in which downward square MFA array processing and upward square MFA array processing are mapped to a one-dimensional array in horizontal directions, respectively. In each PE in the one-dimensional array, downward and upward MFA matrix calculations for two threads are executed. An input and an output are provided for each of PEs at both ends of the one-dimensional array.

Abstract: Disclosed is a signal processing system in a base station that receives and processes single carrier or multiple carrier signals from transmitting units in a sectored coverage area with at least one transmit antenna and at least one receive antenna, the signal power gain between transmit and receive antennas within each sector being represented as a channel matrix with path gains. The system comprises: a detection unit that determines if signals from a given target transmitting unit is available in the signal received in a sector, and generates a detect signal for a combination unit; a decision unit that selects size of interference cancellation matrix; and an interference cancellation unit.

Abstract: The present invention provides an apparatus and a method that realize dynamically processing signals received from multiple sectors to increase throughput of uplink communications in a multi-sectored wireless base station. The signal streams received from sector-1 (25) and (26) and signal streams received from sector-2 (27) and (28) are concentrated in a unit (105). Similarly, channel parameters (29) and (30) from sector-1 and sector-2, respectively, are used to create a modified channel matrix, dimension of which is much larger than that of each of channel matrices of respective sectors. Dynamic processing of signals received from multiple sectors is done by a detection unit (103) which receive channel parameters (131) or (133), and, a comparison unit (104). Signals from a transmitting unit are detected within the signals received from two or more sectors, or the same signals are detected within the signal received from one sector.

Abstract: Disclosed is a CORDIC circuit in which scale correction process is divided into two stages: rough correction and fine correction, and a second-process of a pseudo-rotation process is performed in parallel with the fine scale correction. A range of the fine scale correction is set so that it is not necessary to perform a scale correction with regard to a remaining rotation angle of the first half of the pseudo-rotation process.

Abstract: A linear systolic array is added to the lower side of a trapezoid systolic array created by combining a triangular systolic array and a square systolic array. In order to make the connection among the cells fixed, the intermediate result output from each row of the trapezoid systolic array to a lower row is shifted in phase with respect to the intermediate result of the complex MFA algorithm, the phase shift is absorbed by the next row, and the phase shift in the intermediate result output from the last row of the trapezoid systolic array is corrected by the linear systolic array. Each cell is implemented by a CORDIC circuit that processes vector angle computation, vector rotation, division, and multiply-and-accumulate with a constant delay.

Abstract: To provide a dynamic image receiving apparatus which receives dynamic image streams coded with inter-frame prediction such as MPEG from a plurality of channels, and collects the dynamic image streams containing intra-frame coded pictures from each channel in a short time. The dynamic image receiving apparatus includes: a time information accumulative processing device which accumulates code receiving time of the intra-frame coded picture of the dynamic image stream, and periodicity time information containing one of or both of presentation time information and decoding time information contained in the dynamic image stream for each dynamic image stream of the plurality of channels; code receiving time predicting devices which predict the code receiving time of the intra-frame coded pictures based on the periodicity time information; and a channel selection control device which controls channel selection of the dynamic image stream to be received based on the predicted code receiving time information.