Abstract: The problem of the present invention is to provide a method or the like for producing reduced water (hydrogen-enriched water), which is effective for various diseases caused by active oxygen, more efficiently than the conventional methods, by putting metallic magnesium or the like in water. Adding a metal such as magnesium, together with a solid phase contained in an anode of an oxidation-reduction reaction, to water increases the saturating amount of magnesium ions, and improves deterioration due to magnesium hydroxide being precipitated on the surface of the metallic magnesium. Thus, the abovementioned problem is solved.

Abstract: In a semiconductor integrated circuit, since resistance component is included in a power-supply wiring, a power-supply voltage supplied to a cell on a clock path is dropped to cause a clock skew. To avoid this problem, a cell-placement prohibiting area is set centering on a cell 10 on the clock path, and no cell for performing a logical operation is placed in this cell-placement prohibiting area. Also, a cell-placement prohibiting area may be set for each of cell groups formed of a plurality of cells closely placed together. Furthermore, a capacitive cell may be placed in the cell-placement prohibiting area.

Abstract: In a semiconductor integrated circuit, since resistance component is included in a power-supply wiring, a power-supply voltage supplied to a cell on a clock path is dropped to cause a clock skew. To avoid this problem, a cell-placement prohibiting area is set centering on a cell 10 on the clock path, and no cell for performing a logical operation is placed in this cell-placement prohibiting area. Also, a cell-placement prohibiting area may be set for each of cell groups formed of a plurality of cells closely placed together. Furthermore, a capacitive cell may be placed in the cell-placement prohibiting area.

Abstract: An encryption process is employed in the LSI design so as to improve confidentiality of the circuit design data over conventional examples. In the encryption process, confidential circuit design data is encrypted to produce encrypted design data and a cipher key. The encrypted design data is provided to the user who conducts a design/verification process. The key is also provided as required. In the design/verification process, the encrypted design data is subjected to various processes without disclosing the contents of the original circuit. In a decoding process, the encrypted design data subjected to the design/verification process is decoded to produce original circuit design data.

Abstract: A semiconductor integrated circuit includes a wiring capable of connecting a plurality of chips on a wafer and has a configuration which is capable of cutting the wiring electrically and which allows all the chips to be tested at one time. Specifically, an exclusive test circuit region capable of being shared for testing the plurality of chips is formed on the wafer, and a test circuit is removed from each chip. Terminals of the chips and a terminal of the test circuit are connected through a wiring on the wafer or a device outside the wafer to enable a general test to be performed in burn-in.

Abstract: An encryption process is employed in the LSI design so as to improve confidentiality of the circuit design data over conventional examples. In the encryption process, confidential circuit design data is encrypted to produce encrypted design data and a cipher key. The encrypted design data is provided to the user who conducts a design/verification process. The key is also provided as required. In the design/verification process, the encrypted design data is subjected to various processes without disclosing the contents of the original circuit. In a decoding process, the encrypted design data subjected to the design/verification process is decoded to produce original circuit design data.

Abstract: To provide a semiconductor integrated circuit device in which an occupied area is suppressed from increasing and a high-performance test circuit is included, There is provided a semiconductor integrated circuit having a test circuit, by determining arrangement positions of cells forming a circuit to be tested and non-connected cells prepared to form a test circuit and then determining a connection relationship among the non-connected cells prepared to form the test circuit on the basis of the arrangement information to thereby form the test circuit.

Abstract: A circuit structure analysis unit performs structure analysis for logic circuit information, obtained from an HDL description, and acquires analysis results for function parts, such as a register, an operation unit and a multiplexer. A synthesis instruction generation unit compares the analysis results with a synthesis instruction correlation rule, and automatically generates a synthesis instruction to control a logic synthesis method. Finally, an HDL description output unit outputs a synthesis instruction added HDL description, wherein a synthesis instruction is inserted into the original HDL description. When the synthesis instruction added HDL description is employed in the logic synthesis, starting at the top hierarchical level, a synthesis instruction for the logic circuit is not required in a synthesis execution script.

Abstract: Design data including circuit data on a test point and information about a test mode, which has been attached to the test point, is inputted to an apparatus for designing a semiconductor integrated circuit. A design data code analysis unit in a data input unit performs the code analysis of the design data and, after the code analysis, the resulting design data is stored by a database storage unit in a storage device. A test point deletion unit receives the test mode specified from the outside and deletes data on an unnecessary test point from the design data stored in the storage device. The design data which does not include the unnecessary test point is outputted from a data output unit. Accordingly, even when the test mode is changed, there is no need to calculate the test efficiency again in response to each change or add the step of inserting a new test point.

Abstract: An encryption process is employed in the LSI design so as to improve confidentiality of the circuit design data over conventional examples. In the encryption process, confidential circuit design data is encrypted to produce encrypted design data and a cipher key. The encrypted design data is provided to the user who conducts a design/verification process. The key is also provided as required. In the design/verification process, the encrypted design data is subjected to various processes without disclosing the contents of the original circuit. In a decoding process, the encrypted design data subjected to the design/verification process is decoded to produce original circuit design data.

Abstract: The present invention provides a semiconductor device, in which a plurality of chip IPs are mounted onto a common semiconductor circuit board, an evaluation method for the same, and a function setting method for the same. Various IP groups can be mounted as chip IPs onto a silicon circuit board. The silicon circuit board includes a silicon substrate, a wiring layer and pads. IPs (chip IPs) are mounted onto the pads by lamination. Means for selecting, switching and setting the functions of the IPs are provided, making the semiconductor device suitable for small-variety mass-production.

Abstract: The present invention provides a semiconductor device, in which a plurality of chip IPs are mounted onto a common semiconductor circuit board, an evaluation method for the same, and a function setting method for the same. Various IP groups can be mounted as chip IPs onto a silicon circuit board. The silicon circuit board includes a silicon substrate, a wiring layer and pads. IPs (chip IPs) are mounted onto the pads by lamination. Means for selecting, switching and setting the functions of the IPs are provided, making the semiconductor device suitable for small-variety mass-production.

Abstract: The present invention provides a semiconductor integrated circuit in which timing error is not likely to occur even if there is manufacturing variability. Logic cells 16 and 17, which are included in first and second clock circuits 11 and 12, respectively, are formed by transistors of a unified size. Even if there is manufacturing variability, delay time t1 of the first clock circuit 11 and delay time t2 of the second clock circuit 12 are increased or decreased by the same amount of time. Because of this, timing error is not likely to occur in a second flip-flop 15. A logic cell included in each clock cell may be formed by a transistor having a uniform rectangular-shaped diffusion region.

Abstract: The present invention provides a semiconductor integrated circuit in which timing error is not likely to occur even if there is manufacturing variability. Logic cells 16 and 17, which are included in first and second clock circuits 11 and 12, respectively, are formed by transistors of a unified size. Even if there is manufacturing variability, delay time t1 of the first clock circuit 11 and delay time t2 of the second clock circuit 12 are increased or decreased by the same amount of time. Because of this, timing error is not likely to occur in a second flip-flop 15. A logic cell included in each clock cell may be formed by a transistor having a uniform rectangular-shaped diffusion region.

Abstract: In a semiconductor integrated circuit, since resistance component is included in a power-supply wiring, a power-supply voltage supplied to a cell on a clock path is dropped to cause a clock skew. To avoid this problem, a cell-placement prohibiting area is set centering on a cell 10 on the clock path, and no cell for performing a logical operation is placed in this cell-placement prohibiting area. Also, a cell-placement prohibiting area may be set for each of cell groups formed of a plurality of cells closely placed together. Furthermore, a capacitive cell may be placed in the cell-placement prohibiting area.

Abstract: A circuit from which a buffer and an inverter are removed without changing logic is displayed. Such a circuit is obtained by a first or a second method. With the first method, all buffers which do not change logic and, when a clock path is divided at a branch point of wiring, all pairs of inverters located on each divided clock path are removed from the clock circuit. With the second method, a logic element located on a plurality of clock paths is copied and added to the clock circuit, all buffers which do not change logic and all pairs of inverters located between logic elements other than the above buffers are removed, and redundant partial circuits, if any, realizing the same logic and being located on a plurality of clock paths are removed. Thus, the clock circuit can be displayed so as to facilitate a designer's understanding of logic.

Abstract: The present invention provides a semiconductor integrated circuit in which timing error is not likely to occur even if there is manufacturing variability. Logic cells 16 and 17, which are included in first and second clock circuits 11 and 12, respectively, are formed by transistors of a unified size. Even if there is manufacturing variability, delay time t1 of the first clock circuit 11 and delay time t2 of the second clock circuit 12 are increased or decreased by the same amount of time. Because of this, timing error is not likely to occur in a second flip-flop 15. A logic cell included in each clock cell may be formed by a transistor having a uniform rectangular-shaped diffusion region.

Abstract: A database for design of an integrated circuit device having data stored therein in a flexibly utilizable state, and a method for designing an integrated circuit device using such a database. A virtual core database (VCDB) for storing design data and a VCDB management system (VCDBMS) as a control system are provided. The VCDB includes virtual core (VC) clusters, test vector clusters, and purpose-specific function testing models. The VCDB also includes a system testing database having shared test clusters and peripheral model clusters. The VCDBMS includes a function testing assist section for generating test scenarios, the purpose-specific function testing models, system testing models, and the like, a VC interface synthesis section, and the like.

Abstract: A Treponema pallidum fused antigen in which at least two surface antigens of Treponema pallidum are fused and an assay for anti-Treponema pallidum antibodies, using the above Treponema pallidum fused antigen.

Abstract: An encryption process is employed in the LSI design so as to improve confidentiality of the circuit design data over conventional examples. In the encryption process, confidential circuit design data is encrypted to produce encrypted design data and a cipher key. The encrypted design data is provided to the user who conducts a design/verification process. The key is also provided as required. In the design/verification process, the encrypted design data is subjected to various processes without disclosing the contents of the original circuit. In a decoding process, the encrypted design data subjected to the design/verification process is decoded to produce original circuit design data.