Abstract: Access control is achieved in consideration of write training. Masters issue access requests including a read request and a write request. A memory controller accesses memory in response to the access requests issued by the maters. A central bus-control system controls the output of the access requests issued by the masters to the memory controller. A training circuit conducts training on the memory while the access to the memory is stopped. The central bus-control system further controls the execution of the training on the memory. During the training, the central bus-control system suppresses the output of the read request to the memory controller from among the access requests issued by the masters.

Abstract: Access control is achieved in consideration of write training. Masters issue access requests including a read request and a write request. A memory controller accesses memory in response to the access requests issued by the maters. A central bus-control system controls the output of the access requests issued by the masters to the memory controller. A training circuit conducts training on the memory while the access to the memory is stopped. The central bus-control system further controls the execution of the training on the memory. During the training, the central bus-control system suppresses the output of the read request to the memory controller from among the access requests issued by the masters.

Abstract: Access control is achieved in consideration of write training. Masters issue access requests including a read request and a write request. A memory controller accesses memory in response to the access requests issued by the maters. A central bus-control system controls the output of the access requests issued by the masters to the memory controller. A training circuit conducts training on the memory while the access to the memory is stopped. The central bus-control system further controls the execution of the training on the memory. During the training, the central bus-control system suppresses the output of the read request to the memory controller from among the access requests issued by the masters.

Abstract: Access control is achieved in consideration of write training. Masters issue access requests including a read request and a write request. A memory controller accesses memory in response to the access requests issued by the maters. A central bus-control system controls the output of the access requests issued by the masters to the memory controller. A training circuit conducts training on the memory while the access to the memory is stopped. The central bus-control system further controls the execution of the training on the memory. During the training, the central bus-control system suppresses the output of the read request to the memory controller from among the access requests issued by the masters.

Abstract: An elastic wave device is provided that has an phase velocity optimum for a high-frequency oscillation as well as a preferred frequency temperature behavior that exhibits a cubic curve by utilizing a rotated Y-cut quartz crystal substrate with novel Euler angles of rotation. The elastic wave device includes a quartz crystal substrate and an excitation-electrode. The quartz crystal substrate is cut out from a quartz crystal body that has a particular three-dimensional crystallite orientation. The quartz crystal substrate is cut at rotation angles specified by right-handed Euler-angles. The excitation-electrode generates a plurality of plate waves on a front surface of the quartz crystal substrate. The quartz crystal substrate is cut at rotation angles in a given range. The selected vibration mode of the quartz crystal substrate is a plate wave having a primary and a secondary temperature coefficient in given ranges with Taylor expansion performed at a particular temperature.

Abstract: An elastic wave device is provided that has an phase velocity optimum for a high-frequency oscillation as well as a preferred frequency temperature behavior that exhibits a cubic curve by utilizing a rotated Y-cut quartz crystal substrate with novel Euler angles of rotation. The elastic wave device includes a quartz crystal substrate and an excitation-electrode. The quartz crystal substrate is cut out from a quartz crystal body that has a particular three-dimensional crystallite orientation. The quartz crystal substrate is cut at rotation angles specified by right-handed Euler-angles. The excitation-electrode generates a plurality of plate waves on a front surface of the quartz crystal substrate. The quartz crystal substrate is cut at rotation angles in a given range. The selected vibration mode of the quartz crystal substrate is a plate wave having a primary and a secondary temperature coefficient in given ranges with Taylor expansion performed at a particular temperature.

Abstract: The present invention provides a data processing apparatus realizing reduced load on a host CPU and improved performance. An arithmetic unit includes an SIMD processor for processing a plurality of pieces of data by a single instruction, and a second CPU coupled to the SIMD processor via an arithmetic unit bus and controlling the SIMD processor. A host system includes a host CPU for controlling the entire data processing apparatus, a built-in memory and a peripheral circuit coupled to the host CPU via a first bus, and a peripheral circuit coupled to a second bus. The second CPU accesses an external flash/ROM via the arithmetic unit bus and the first bus, and the SIMD processor accesses an external memory via the second bus. Therefore, the load on the host CPU can be reduced, and the performance of the entire apparatus can be improved.

Abstract: In arithmetic/logic units (ALU) provided corresponding to entries, an MIMD instruction decoder generating a group of control signals in accordance with a Multiple Instruction-Multiple Data (MIMD) instruction and an MIMD register storing data designating the MIMD instruction are provided, and an inter-ALU communication circuit is provided. The amount and direction of movement of the inter-ALU communication circuit are set by data bits stored in a movement data register. It is possible to execute data movement and arithmetic/logic operation with the amount of movement and operation instruction set individually for each ALU unit. Therefore, in a Single Instruction-Multiple Data type processing device, Multiple Instruction-Multiple Data operation can be executed at high speed in a flexible manner.

Abstract: In arithmetic/logic units (ALU) provided corresponding to entries, an MIMD instruction decoder generating a group of control signals in accordance with a Multiple Instruction-Multiple Data (MIMD) instruction and an MIMD register storing data designating the MIMD instruction are provided, and an inter-ALU communication circuit is provided. The amount and direction of movement of the inter-ALU communication circuit are set by data bits stored in a movement data register. It is possible to execute data movement and arithmetic/logic operation with the amount of movement and operation instruction set individually for each ALU unit. Therefore, in a Single Instruction-Multiple Data type processing device, Multiple Instruction-Multiple Data operation can be executed at high speed in a flexible manner.

Abstract: The present invention provides a data processing apparatus realizing reduced load on a host CPU and improved performance. An arithmetic unit includes an SIMD processor for processing a plurality of pieces of data by a single instruction, and a second CPU coupled to the SIMD processor via an arithmetic unit bus and controlling the SIMD processor. A host system includes a host CPU for controlling the entire data processing apparatus, a built-in memory and a peripheral circuit coupled to the host CPU via a first bus, and a peripheral circuit coupled to a second bus. The second CPU accesses an external flash/ROM via the arithmetic unit bus and the first bus, and the SIMD processor accesses an external memory via the second bus. Therefore, the load on the host CPU can be reduced, and the performance of the entire apparatus can be improved.

Abstract: In arithmetic/logic units (ALU) provided corresponding to entries, an MIMD instruction decoder generating a group of control signals in accordance with a Multiple Instruction Multiple Data (MIME) instruction and an MIMD register storing data designating the MIME instruction are provided, and an inter-ALU communication circuit is provided. The amount and direction of movement of the inter-ALU communication circuit are set by data bits stored in a movement data register. It is possible to execute data movement and arithmetic/logic operation with the amount of movement and operation instruction set individually for each ALU unit Therefore, in a Single Instruction-Multiple Data type processing device, Multiple Instruction-Multiple Data operation can be executed at high speed in a flexible manner.

Abstract: A data/clock recovery circuit can recover high-rate data using the data as a clock signal. It includes an edge detector, a clock selection signal generating circuit, a clock selection circuit and a synchronizing circuit. The edge detector generates edge position information using a receiver output as a clock signal. The clock selection signal generating circuit generates a clock selection signal in response to the edge position information using the receiver output as the clock signal. The clock selection circuit selects a recovered clock signal from a clock signal group in response to the clock selection signal. The synchronizing circuit synchronizes the receiver output using the recovered clock signal, and outputs it as a synchronized data signal.

Abstract: The number of pulses of a clock signal CLK-A is circularly counted in a count range from “0” to “7”, and count signals indicating count values are produced. A clock signal CLK-B having a frequency lower than that of the clock signal CLK-A is produced from count signals of “3” and “7”, and data transfer between a high speed operating block operated in synchronization with the clock signal CLK-A and a low speed operating block operated in synchronization with the clock signal CLK-B is performed in synchronization with the clock signal CLK-B to receive input serial data or transmit output serial data. When a stuff bit of universal Serial Bus is detected in the input serial data or is inserted in the output serial data, a cycle of the clock signal CLK-B is lengthened by one cycle of the clock signal CLK-A.

Abstract: The number of pulses of a clock signal CLK-A is circularly counted in a count range from “0” to “7”, and count signals indicating count values are produced. A clock signal CLK-B having a frequency lower than that of the clock signal CLK-A is produced from count signals of “3” and “7”, and data transfer between a high speed operating block operated in synchronization with the clock signal CLK-A and a low speed operating block operated in synchronization with the clock signal CLK-B is performed in synchronization with the clock signal CLK-B to receive input serial data or transmit output serial data. When a stuff bit of universal Serial Bus is detected in the input serial data or is inserted in the output serial data, a cycle of the clock signal CLK-B is lengthened by one cycle of the clock signal CLK-A.

Abstract: A data/clock recovery circuit can recover high-rate data using the data as a clock signal. It includes an edge detector, a clock selection signal generating circuit, a clock selection circuit and a synchronizing circuit. The edge detector generates edge position information using a receiver output as a clock signal. The clock selection signal generating circuit generates a clock selection signal in response to the edge position information using the receiver output as the clock signal. The clock selection circuit selects a recovered clock signal from a clock signal group in response to the clock selection signal. The synchronizing circuit synchronizes the receiver output using the recovered clock signal, and outputs it as a synchronized data signal.

Abstract: A source-level debugger debugs a source program for computers using a pipeline control method. The debugger includes a not-yet-processed instruction analyzing unit for analyzing each of instructions including not-yet-process stages in a pipeline when execution of a source program is halted (or suspended) or terminated, and for acquiring information on an internal state of the pipeline. A user interface unit displays the information on the internal state of the pipeline acquired by the not-yet-processed instruction analyzing unit in a predetermined display form on the screen of a display unit.