Patents by Inventor Katsuya Nakamoto

Katsuya Nakamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8010872
    Abstract: The invention improves safety of an electronic controller using a nonvolatile memory MRAM able to easily perform reading and writing operations at high speed. Therefore, MRAM for writing a control program from an external tool has a correction code adding writing circuit, a decoding reading-out circuit, and error registers for writing an error generating address number thereto as error data. When the error generating address is designated and confirmation reading-out is performed and an error is generated as before, an overlapping abnormality judgment is made and abnormality notification is performed. A program memory area of MRAM is normally in a writing inhibition state. When the external tool is connected, the inhibition state is released. The error registers are arranged in a data memory area set to no writing inhibition object.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: August 30, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventors: Koji Hashimoto, Katsuya Nakamoto, Shoso Tsunekazu, Shinsuke Suzuki
  • Publication number: 20080162854
    Abstract: The invention improves safety of an electronic controller using a nonvolatile memory MRAM able to easily perform reading and writing operations at high speed. Therefore, MRAM for writing a control program from an external tool has a correction code adding writing circuit, a decoding reading-out circuit, and error registers for writing an error generating address number thereto as error data. When the error generating address is designated and confirmation reading-out is performed and an error is generated as before, an overlapping abnormality judgment is made and abnormality notification is performed. A program memory area of MRAM is normally in a writing inhibition state. When the external tool is connected, the inhibition state is released. The error registers are arranged in a data memory area set to no writing inhibition object.
    Type: Application
    Filed: August 29, 2007
    Publication date: July 3, 2008
    Applicant: Mitsubishi Electric Corporation
    Inventors: Koji HASHIMOTO, Katsuya Nakamoto, Shoso Tsunekazu, Shinsuke Suzuki
  • Patent number: 7346002
    Abstract: A first control circuit section (master station) and a second control circuit section (substation) communicate with each other via series-parallel converters. The master station includes regular transmission device and transmission-permitting signal generation device; and the sub station includes regular report device, confirmation reply device relative to a transmission data from the master station, and an unprocessed data table. The unprocessed data table prevents jam-up in upstream communication from the sub station to the master station, enabling to carry out timely regular transmission and regular reporting. Transmission from the sub station to the master station is performed based on a transmission-permitting control signal that the master station generates. Consequently, it is possible to execute communication error processing and diminish communication control burden on the master station while properly performing the regular transmission and regular report between the master station and sub station.
    Type: Grant
    Filed: May 17, 2004
    Date of Patent: March 18, 2008
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kohji Hashimoto, Katsuya Nakamoto, Yuki Iwagami, Akihiro Ishii
  • Patent number: 7287183
    Abstract: First and second control circuit sections that mutually communicate via a series-parallel converter comprise first and second adder-subtracter respectively. When any receiving error occurs in each control circuit section, a variation value 3 is added to the adder-subtracter on the receiving side. When data is normally received, a variation value 1 is subtracted from the adder-subtracter. Initial value of the adder-subtracter is set to 9. When a current value exceeds 11, first and second error detection signal is generated to carry out alarm display or initialization, and initialization and restart of the other-side control circuit section.
    Type: Grant
    Filed: March 1, 2004
    Date of Patent: October 23, 2007
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kohji Hashimoto, Katsuya Nakamoto, Yuki Iwagami, Akihiro Ishii
  • Patent number: 7251551
    Abstract: An on-vehicle electronic control device includes an auxiliary microprocessor and subjects a microprocessor allocated to a main part of control to an external diagnosis, thereby improving reliability of performance. A microprocessor including a nonvolatile program memory into which a control program is written is serially connected to an auxiliary microprocessor including an auxiliary nonvolatile program memory. The microprocessor and the auxiliary microprocessor function in cooperation to control on-vehicle electric load groups in response to input signals from on-vehicle sensor groups and on-vehicle analog sensor group. The nonvolatile program memory and the microprocessor are subjected to runaway monitoring performed by a watchdog timer and to an external checksum diagnosis performed periodically by the auxiliary microprocessor. If an anomaly occurs in the runaway monitoring, the external checksum diagnosis, and a checksum interval, parts of electric loads are cut off of power supply by load power relay.
    Type: Grant
    Filed: June 4, 2004
    Date of Patent: July 31, 2007
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroyuki Mitsueda, Katsuya Nakamoto, Kohji Hashimoto
  • Patent number: 7178069
    Abstract: An electronic control unit includes a serial communication circuit capable of easily confirming presence or absence of communication error while regular transmission/regular report between master station and sub station are performed timely. First and second control circuit sections 200a (master station) and 200b (substation) communicate mutually via series-parallel converters 117, 127. The master station includes regular transmission device 201 and irregular transmission device 211. The substation includes regular report device 221, confirmation reply device 205 and report reply device 215 relative to transmission data from the master station, and unprocessed data table 204. The confirmation reply device 205 and report reply device 215 confirm whether or not downstream communication from the master station to sub station is normal.
    Type: Grant
    Filed: March 1, 2004
    Date of Patent: February 13, 2007
    Assignee: Mitsubishi Denki Kabushiki Kasiha
    Inventors: Kohji Hashimoto, Katsuya Nakamoto, Yuki Iwagami, Akihiro Ishii
  • Patent number: 7121258
    Abstract: Intake throttle valves 21a to 21d disposed on the intake pipes 15a to 15d for each cylinder of a multi-cylinder engine 10 are provided with motors 20a to 20d for controlling valve opening of the intake throttle valves. The microprocessor 31 controls throttle valve opening in response to a degree of stepping on an accelerator pedal 42 in cooperation with a program memory 32A. The control of valve opening by each motor is sequentially subject to time division processing in the exhaust stroke of each cylinder, and a current valve opening is stored and held by a feedback control circuit section 39, 69B, 69C in the other strokes, thereby the control burden on the microprocessor being reduced.
    Type: Grant
    Filed: March 1, 2005
    Date of Patent: October 17, 2006
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsuya Nakamoto, Kohji Hashimoto
  • Patent number: 7107488
    Abstract: A microprocessor 20a controls an electrical load group 12 responsive to content of a non-volatile program memory 25a and operation state of an input sensor group 11. A monitoring control circuit section 30a sequentially transmits a large number of question items with an inquiry packet, and compares response content from the microprocessor 20a with correct answer information to carry out an error determination. The microprocessor 20a diagnoses an interval of receiving an inquiry packet to monitor in reverse the monitoring operation of the monitoring control circuit section 30a. Thus, in an electronic control unit having a microprocessor built-in, a monitoring control circuit is obtained that alternatively executes at regular intervals a part of control programs to carry out operation inspection during operation.
    Type: Grant
    Filed: January 16, 2004
    Date of Patent: September 12, 2006
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kohji Hashimoto, Katsuya Nakamoto
  • Patent number: 7031822
    Abstract: In an on-vehicle electronic control unit, error in output voltages from a constant voltage power supply circuit (C.V.P.S.) for use in a reference power supply of an A/D converter, occurs due to temperature rise. Whereby, there is a problem of the decrease of an A/D conversion accuracy. A C.V.P.S. supplies a voltage to analog sensors and to an AD converter. Furthermore, an output from a temperature sensor that is disposed in the neighborhood of the C.V.P.S. is stored in a memory as a contrast temperature data T at a time point of shipping. In addition, voltage fluctuation characteristic data due to the change of temperatures of the C.V.P.S. and detection fluctuation characteristic data accompanied by the change of voltages of the analog sensor group have preliminarily been stored, and the fluctuations in digital converted values accompanied with the change of temperatures in the neighborhood of the C.V.P.S. are compensated.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: April 18, 2006
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kohji Hashimoto, Katsuya Nakamoto, Yasuhiko Kannan
  • Publication number: 20060042593
    Abstract: Intake throttle valves 21a to 21d disposed on the intake pipes 15a to 15d for each cylinder of a multi-cylinder engine 10 are provided with motors 20a to 20d for controlling valve opening of the intake throttle valves. The microprocessor 31 controls throttle valve opening in response to a degree of stepping on an accelerator pedal 42 in cooperation with a program memory 32A. The control of valve opening by each motor is sequentially subject to time division processing in the exhaust stroke of each cylinder, and a current valve opening is stored and held by a feedback control circuit section 39, 69B, 69C in the other strokes, thereby the control burden on the microprocessor being reduced.
    Type: Application
    Filed: March 1, 2005
    Publication date: March 2, 2006
    Inventors: Katsuya Nakamoto, Kohji Hashimoto
  • Publication number: 20050199215
    Abstract: An operation control device of a multi-cylinder engine having a long life and low power consumption is superior in acceleration/deceleration follow-up characteristic. Individual cylinder intake pipes 15a to 15d of a multi-cylinder engine 10 controlled by an operation control device 30a, and provided with cylinders 10a, 10b, 10c, 10d are provided with throttle valves 21a to 21d of which valve openings are controlled by motors 20a to 20d. The operation control device 30a including a microprocessor 31, a program memory 32a, and a data memory 33 performs an ON/OFF control of the motors 20a to 20d of individual cylinders in accordance with a corrective data stored in the data memory 33 for correcting an air intake resistance fluctuation in each individual cylinder intake pipe and a depression degree of an accelerator pedal.
    Type: Application
    Filed: September 9, 2004
    Publication date: September 15, 2005
    Inventors: Katsuya Nakamoto, Kohji Hashimoto
  • Patent number: 6935308
    Abstract: An operation control device of a multi-cylinder engine having a long life and low power consumption is superior in acceleration/deceleration follow-up characteristic. Individual cylinder intake pipes 15a to 15d of a multi-cylinder engine 10 controlled by an operation control device 30a, and provided with cylinders 10a, 10b, 10c, 10d are provided with throttle valves 21a to 21d of which valve openings are controlled by motors 20a to 20d. The operation control device 30a including a microprocessor 31, a program memory 32a, and a data memory 33 performs an ON/OFF control of the motors 20a to 20d of individual cylinders in accordance with a corrective data stored in the data memory 33 for correcting an air intake resistance fluctuation in each individual cylinder intake pipe and a depression degree of an accelerator pedal.
    Type: Grant
    Filed: September 9, 2004
    Date of Patent: August 30, 2005
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsuya Nakamoto, Kohji Hashimoto
  • Patent number: 6915192
    Abstract: A vehicular electronic control apparatus is provided with a program memory, a data memory, a RAM, a microprocesser, a reference data storage memory, a data memory abnormality judging section, and at least two transfer sections for a RAM. The reference data storage memory stores reference data corresponding to variable control data stored in the data memory. The data memory abnormality judging section judges whether the variable control data stored in the data memory are normal or abnormal. The first transfer section transfers and writes the variable control data from the data memory to the RAM. The second transfer section writes estimated variable control data based on the reference data from the reference data storage memory to the RAM.
    Type: Grant
    Filed: August 7, 2003
    Date of Patent: July 5, 2005
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kohji Hashimoto, Katsuya Nakamoto
  • Publication number: 20050085967
    Abstract: An on-vehicle electronic control device is provided, which includes an auxiliary microprocessor and subjects a microprocessor allocated to a main part of control to an external diagnosis, thereby improving reliability of performance. A microprocessor (110a) including a nonvolatile program memory (115a) into which a control program is written is serially connected to an auxiliary microprocessor (120a) including an auxiliary nonvolatile program memory (125). The microprocessor (110a) and the auxiliary microprocessor (120a) functions in cooperation to control on-vehicle electric load groups (104a and 104b) in response to input signals from on-vehicle sensor groups (102a and 102b) and an on-vehicle analog sensor group 103a. The nonvolatile program memory (115a) and the microprocessor (110a) are subjected to runaway monitoring performed by a watchdog timer (130) and to an external checksum diagnosis performed periodically by the auxiliary microprocessor (120a).
    Type: Application
    Filed: June 4, 2004
    Publication date: April 21, 2005
    Inventors: Hiroyuki Mitsueda, Katsuya Nakamoto, Kohji Hashimoto
  • Patent number: 6883123
    Abstract: A microprocessor runaway monitoring control circuit with which self-diagnosis of a watchdog timer WDT can be carried out safely and cheaply even during operation of the microprocessor (CPU). A microprocessor 101 supplies first and second watchdog clearing signals WD1 and WD2 to first and second watchdog timers WDT1 and WDT2, and when the both of the watchdog clearing signals WD1 and WD2 stop, the microprocessor 101 is reset by way of a logical connector circuit 122. The microprocessor 101 has failure diagnosing means 103 which intentionally stops the first watchdog clearing signal WD1 and diagnoses the response of the first watchdog timer WDT1 on the basis of a monitor signal MN1 and stops the second watchdog clearing signal WD2 and diagnoses the response of the second watchdog timer WDT2 on the basis of a monitor signal MN2, whereby diagnosis of the watchdog timers WDT1, WDT2 is carried out without the microprocessor 101 being stopped.
    Type: Grant
    Filed: April 23, 2002
    Date of Patent: April 19, 2005
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kohji Hashimoto, Katsuya Nakamoto, Masahide Fujita, Hiroyuki Mitsueda
  • Publication number: 20050080529
    Abstract: A first control circuit section (master station) and a second control circuit section (substation) communicate with each other via series-parallel converters. The master station includes regular transmission device and transmission-permitting signal generation device; and the sub station includes regular report device, confirmation reply device relative to a transmission data from the master station, and an unprocessed data table. The unprocessed data table prevents jam-up in upstream communication from the sub station to the master station, enabling to carry out timely regular transmission and regular reporting. Transmission from the sub station to the master station is performed based on a transmission-permitting control signal that the master station generates. Consequently, it is possible to execute communication error processing and diminish communication control burden on the master station while properly performing the regular transmission and regular report between the master station and sub station.
    Type: Application
    Filed: May 17, 2004
    Publication date: April 14, 2005
    Inventors: Kohji Hashimoto, Katsuya Nakamoto, Yuki Iwagami, Akihiro Ishii
  • Publication number: 20050034015
    Abstract: An electronic control unit includes a serial communication circuit capable of easily confirming presence or absence of communication error while regular transmission/regular report between master station and sub station are performed timely. First and second control circuit sections 200a (master station) and 200b (substation) communicate mutually via series-parallel converters 117, 127. The master station includes regular transmission device 201 and irregular transmission device 211. The substation includes regular report device 221, confirmation reply device 205 and report reply device 215 relative to transmission data from the master station, and unprocessed data table 204. The confirmation reply device 205 and report reply device 215 confirm whether or not downstream communication from the master station to sub station is normal.
    Type: Application
    Filed: March 1, 2004
    Publication date: February 10, 2005
    Inventors: Kohji Hashimoto, Katsuya Nakamoto, Yuki Iwagami, Akihiro Ishii
  • Publication number: 20050022060
    Abstract: A microprocessor 20a controls an electrical load group 12 responsive to content of a non-volatile program memory 25a and operation state of an input sensor group 11. A monitoring control circuit section 30a sequentially transmits a large number of question items with an inquiry packet, and compares response content from the microprocessor 20a with correct answer information to carry out an error determination. The microprocessor 20a diagnoses an interval of receiving an inquiry packet to monitor in reverse the monitoring operation of the monitoring control circuit section 30a. Thus, in an electronic control unit having a microprocessor built-in, a monitoring control circuit is obtained that alternatively executes at regular intervals a part of control programs to carry out operation inspection during operation.
    Type: Application
    Filed: January 16, 2004
    Publication date: January 27, 2005
    Inventors: Kohji Hashimoto, Katsuya Nakamoto
  • Publication number: 20050015160
    Abstract: First and second control circuit sections that mutually communicate via a series-parallel converter comprise first and second adder-subtracter respectively. When any receiving error occurs in each control circuit section, a variation value 3 is added to the adder-subtracter on the receiving side. When data is normally received, a variation value 1 is subtracted from the adder-subtradcter. Initial value of the adder-subtracter is set to 9. When a current value exceeds 11, first and second error detection signal is generated to carry out alarm display or initialization, and initialization and restart of the other-side control circuit section.
    Type: Application
    Filed: March 1, 2004
    Publication date: January 20, 2005
    Inventors: Kohji Hashimoto, Katsuya Nakamoto, Yuki Iwagami, Akihiro Ishii
  • Patent number: 6845315
    Abstract: A drive control circuit generates a conduction drive output responsive to a detection output of an accelerator pedal depression degree sensor and an air-intake throttle-valve opening sensor, and controls a driving switch element connected to an air-intake throttle-valve opening control motor. A monitoring control circuit drives a control circuit power supply interruption element that closes a control power supply circuit of the driving switch element, and stops control operation of the driving switch element by a conduction-inhibit output. The drive control circuit can stop operation of a power supply interruption element by a feed-inhibit output. At the time of starting operation, a status signal determines activeness of the feed-inhibit output and conduction-inhibit output, after confirming that those outputs are normal, the inhibition is released.
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: January 18, 2005
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kohji Hashimoto, Katsuya Nakamoto