Patents by Inventor Katsuyoshi Mitsui
Katsuyoshi Mitsui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9467090Abstract: A semiconductor device contrived to prevent a reference voltage and a reference current which are supplied to a high speed OCO from varying with a change in ambient temperature and/or a change in an external power supply voltage and to reduce the circuit area of a power supply module. The high speed OCO outputs a high speed clock whose magnitude is determined by the reference current and the reference voltage. A logic unit adjusts the values of the reference current and reference voltage, according to the reference voltage and reference current trimming codes related to detected ambient temperature and operating voltage.Type: GrantFiled: January 9, 2015Date of Patent: October 11, 2016Assignee: Renesas Electronics CorporationInventors: Tsukasa Oishi, Katsuyoshi Mitsui, Naoki Otani
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Publication number: 20150116041Abstract: A semiconductor device contrived to prevent a reference voltage and a reference current which are supplied to a high speed OCO from varying with a change in ambient temperature and/or a change in an external power supply voltage and to reduce the circuit area of a power supply module. The high speed OCO outputs a high speed clock whose magnitude is determined by the reference current and the reference voltage. A logic unit adjusts the values of the reference current and reference voltage, according to the reference voltage and reference current trimming codes related to detected ambient temperature and operating voltage.Type: ApplicationFiled: January 9, 2015Publication date: April 30, 2015Inventors: Tsukasa OISHI, Katsuyoshi MITSUI, Naoki OTANI
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Patent number: 8963650Abstract: A semiconductor device contrived to prevent a reference voltage and a reference current which are supplied to a high speed OCO from varying with a change in ambient temperature and/or a change in an external power supply voltage and to reduce the circuit area of a power supply module. The high speed OCO outputs a high speed clock whose magnitude is determined by the reference current and the reference voltage. A logic unit adjusts the values of the reference current and reference voltage, according to the reference voltage and reference current trimming codes related to detected ambient temperature and operating voltage.Type: GrantFiled: August 9, 2012Date of Patent: February 24, 2015Assignee: Renesas Electronics CorporationInventors: Tsukasa Oishi, Katsuyoshi Mitsui, Naoki Otani
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Publication number: 20120299663Abstract: A semiconductor device contrived to prevent a reference voltage and a reference current which are supplied to a high speed OCO from varying with a change in ambient temperature and/or a change in an external power supply voltage and to reduce the circuit area of a power supply module. The high speed OCO outputs a high speed clock whose magnitude is determined by the reference current and the reference voltage. A logic unit adjusts the values of the reference current and reference voltage, according to the reference voltage and reference current trimming codes related to detected ambient temperature and operating voltage.Type: ApplicationFiled: August 9, 2012Publication date: November 29, 2012Inventors: Tsukasa OISHI, Katsuyoshi Mitsui, Naoki Otani
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Patent number: 8264294Abstract: A semiconductor device contrived to prevent a reference voltage and a reference current which are supplied to a high speed OCO from varying with a change in ambient temperature and/or a change in an external power supply voltage and to reduce the circuit area of a power supply module. The high speed OCO outputs a high speed clock whose magnitude is determined by the reference current and the reference voltage. A logic unit adjusts the values of the reference current and reference voltage, according to the reference voltage and reference current trimming codes related to detected ambient temperature and operating voltage.Type: GrantFiled: February 4, 2011Date of Patent: September 11, 2012Assignee: Renesas Electronics CorporationInventors: Tsukasa Oishi, Katsuyoshi Mitsui, Naoki Otani
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Publication number: 20110193640Abstract: This invention provides a semiconductor device contrived to prevent a reference voltage and a reference current which are supplied to a high speed OCO from varying with a change in ambient temperature and/or a change in an external power supply voltage and to reduce the circuit area of a power supply module. The high speed OCO outputs a high speed clock whose magnitude is determined by the reference current and the reference voltage. A temperature sensor detects the ambient temperature of the high speed OCO and a voltage sensor detects the operating voltage of the high speed OCO. The power supply module includes a BGR and generates the reference voltage, reference current, and operating voltage of the high speed OCO, based on a primary reference voltage which is output by the BGR. A flash memory stores a table specifying trimming codes for the reference voltage and reference current, related to an ambient temperature and an operating voltage of the high speed OCO.Type: ApplicationFiled: February 4, 2011Publication date: August 11, 2011Inventors: Tsukasa OISHI, Katsuyoshi Mitsui, Naoki Otani
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Patent number: 7728678Abstract: A semiconductor device includes a voltage control and oscillation circuit oscillating at a frequency according to a first control voltage to output an oscillation signal, a frequency/voltage conversion circuit receiving the oscillation signal from the voltage control and oscillation circuit and converting a frequency of the oscillation signal into a voltage, a control voltage generation circuit generating a new second control voltage having a level between that of the voltage converted by the frequency/voltage conversion circuit and that of a second control voltage generated previously, and an analog integration circuit integrating the second control voltage to generate the first control voltage and outputting the first control voltage to the voltage control and oscillation circuit.Type: GrantFiled: October 17, 2008Date of Patent: June 1, 2010Assignee: Renesas Technology Corp.Inventor: Katsuyoshi Mitsui
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Publication number: 20090128243Abstract: A semiconductor device includes a voltage control and oscillation circuit oscillating at a frequency according to a first control voltage to output an oscillation signal, a frequency/voltage conversion circuit receiving the oscillation signal from the voltage control and oscillation circuit and converting a frequency of the oscillation signal into a voltage, a control voltage generation circuit generating a new second control voltage having a level between that of the voltage converted by the frequency/voltage conversion circuit and that of a second control voltage generated previously, and an analog integration circuit integrating the second control voltage to generate the first control voltage and outputting the first control voltage to the voltage control and oscillation circuit.Type: ApplicationFiled: October 17, 2008Publication date: May 21, 2009Inventor: Katsuyoshi MITSUI
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Patent number: 6937088Abstract: An internal power supply potential generating circuit includes: a control potential generating circuit having four MOS transistors connected in series between a node and a ground potential line, and controlling a pull-up transistor and a pull-down transistor in order that a potential at an output node coincides with a control potential; a monitor potential generating circuit having four MOS transistors connected in series between a prescribed node and a ground potential line, and generating a monitor potential; a potential dividing circuit generating a potential ½ times a reference potential; and a VCC1 generating circuit controlling a potential at the prescribed potential in order that the monitor potential becomes the reference potential. Therefore, an output potential can be controlled with correctness.Type: GrantFiled: August 3, 2004Date of Patent: August 30, 2005Assignee: Renesas Technology Corp.Inventors: Takeshi Hamamoto, Katsuyoshi Mitsui
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Publication number: 20050007190Abstract: An internal power supply potential generating circuit includes: a control potential generating circuit having four MOS transistors connected in series between a node and a ground potential line, and controlling a pull-up transistor and a pull-down transistor in order that a potential at an output node coincides with a control potential; a monitor potential generating circuit having four MOS transistors connected in series between a prescribed node and a ground potential line, and generating a monitor potential; a potential dividing circuit generating a potential 1/2 times a reference potential; and a VCC1 generating circuit controlling a potential at the prescribed potential in order that the monitor potential becomes the reference potential. Therefore, an output potential can be controlled with correctness.Type: ApplicationFiled: August 3, 2004Publication date: January 13, 2005Applicant: RENESAS TECHNOLOGY CORP.Inventors: Takeshi Hamamoto, Katsuyoshi Mitsui
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Patent number: 6812748Abstract: A VBB control circuit includes an intermediate potential generation circuit receiving a substrate potential VBB which is a negative potential and outputting a divided potential between a power supply potential INTVDD and a ground potential, and an inverter receiving the divided potential and determining whether the substrate potential is higher or lower than a desired value. A logic threshold value of the inverter is (½)×INTVDD. If a relationship of VBB=VREFB−(½)×INTVDD is satisfied, the divided potential accurately becomes (½)×INTVDD. Thereby, it is possible to realize a semiconductor device including a detection circuit which can arbitrarily select a detected potential of the VBB by changing VREFB and which is less influenced by a change in manufacturing conditions.Type: GrantFiled: December 31, 2002Date of Patent: November 2, 2004Assignee: Renesas Technology Corp.Inventor: Katsuyoshi Mitsui
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Patent number: 6781443Abstract: An internal power supply potential generating circuit includes: a control potential generating circuit having four MOS transistors connected in series between a node and a ground potential line, and controlling a pull-up transistor and a pull-down transistor in order that a potential at an output node coincides with a control potential; a monitor potential generating circuit having four MOS transistors connected in series between a prescribed node and a ground potential line, and generating a monitor potential; a potential dividing circuit generating a potential 1/2 times a reference potential; and a VCC1 generating circuit controlling a potential at the prescribed potential in order that the monitor potential becomes the reference potential. Therefore, an output potential can be controlled with correctness.Type: GrantFiled: October 22, 2002Date of Patent: August 24, 2004Assignee: Renesas Technology Corp.Inventors: Takeshi Hamamoto, Katsuyoshi Mitsui
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Patent number: 6765432Abstract: In a semiconductor device, a time-counting circuit counting a prescribed time in transition to a low-power operation mode includes a CR-type time constant circuit and a complementary NOR gate. The time-counting circuit causes electric charges to be released from a capacitive element through a resistance element when a prescribed signal attains L level. As release of the electric charges continues, the NOR gate operates, a power control signal is output at L level, and the semiconductor device makes a transition to the low-power operation mode. Thus, since the time-counting circuit does not include a multi-stage delay circuit and a latch circuit for time-count, power consumption is low, and circuit area is small. Consequently, the semiconductor device capable of transition to the low-power operation mode can simultaneously implement lower power consumption and smaller circuit area.Type: GrantFiled: January 3, 2003Date of Patent: July 20, 2004Assignee: Renesas Technology Corp.Inventor: Katsuyoshi Mitsui
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Patent number: 6753720Abstract: In order to stably generate a high voltage of a prescribed level, a Vpp detection circuit which is activated in response to an activation signal for comparing the high voltage with a reference voltage is forcibly brought into an active state for a prescribed period under control of an initial control circuit.Type: GrantFiled: November 25, 2002Date of Patent: June 22, 2004Assignee: Renesas Technology Corp.Inventors: Takashi Kono, Katsuyoshi Mitsui, Kiyohiro Furutani
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Patent number: 6714065Abstract: The boosting circuit provided in a semiconductor device includes a ring oscillator generating a pump clock having constant periods, a pump capacitor for performing a boost operation, and a pump capacitor input control unit provided between one electrode of the pump capacitor and the ring oscillator. The pump capacitor input control unit fixes one electrode of the pump capacitor to a prescribed voltage to apply stress of a desired level to the pump capacitor in response to a control signal that is activated at the time of burn-in test.Type: GrantFiled: October 26, 2001Date of Patent: March 30, 2004Assignee: Renesas Technology Corp.Inventors: Yuichiro Komiya, Katsuyoshi Mitsui
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Publication number: 20040008076Abstract: A VBB control circuit includes an intermediate potential generation circuit receiving a substrate potential VBB which is a negative potential and outputting a divided potential between a power supply potential INTVDD and a ground potential, and an inverter receiving the divided potential and determining whether the substrate potential is higher or lower than a desired value. A logic threshold value of the inverter is (½)×INTVDD. If a relationship of VBB=VREFB−(½)×INTVDD is satisfied, the divided potential accurately becomes (½)×INTVDD. Thereby, it is possible to realize a semiconductor device including a detection circuit which can arbitrarily select a detected potential of the VBB by changing VREFB and which is less influenced by a change in manufacturing conditions.Type: ApplicationFiled: December 31, 2002Publication date: January 15, 2004Inventor: Katsuyoshi Mitsui
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Publication number: 20040000946Abstract: In a semiconductor device, a time-counting circuit counting a prescribed time in transition to a low-power operation mode includes a CR-type time constant circuit and a complementary NOR gate. The time-counting circuit causes electric charges to be released from a capacitive element through a resistance element when a prescribed signal attains L level. As release of the electric charges continues, the NOR gate operates, a power control signal is output at L level, and the semiconductor device makes a transition to the low-power operation mode. Thus, since the time-counting circuit does not include a multi-stage delay circuit and a latch circuit for time-count, power consumption is low, and circuit area is small. Consequently, the semiconductor device capable of transition to the low-power operation mode can simultaneously implement lower power consumption and smaller circuit area.Type: ApplicationFiled: January 3, 2003Publication date: January 1, 2004Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventor: Katsuyoshi Mitsui
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Publication number: 20030197551Abstract: An internal power supply potential generating circuit includes: a control potential generating circuit having four MOS transistors connected in series between a node and a ground potential line, and controlling a pull-up transistor and a pull-down transistor in order that a potential at an output node coincides with a control potential; a monitor potential generating circuit having four MOS transistors connected in series between a prescribed node and a ground potential line, and generating a monitor potential; a potential dividing circuit generating a potential 1/2 times a reference potential; and a VCC1 generating circuit controlling a potential at the prescribed potential in order that the monitor potential becomes the reference potential. Therefore, an output potential can be controlled with correctness.Type: ApplicationFiled: October 22, 2002Publication date: October 23, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Takeshi Hamamoto, Katsuyoshi Mitsui
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Patent number: 6603695Abstract: An address generating circuit of a DRAM includes five fuses, a trimming switching circuit generating five signals in accordance with whether or not each fuse is blown, a voltage converting circuit generating a control voltage of a level corresponding to the five signals, a voltage control oscillation circuit generating a clock signal of a cycle according to the control voltage, and an address counter generating an address signal in synchronization with the clock signal. Thus, unlike a conventional example, a plurality of counting circuits and a detection circuit are eliminated, resulting in reduction of power consumption and circuit scale.Type: GrantFiled: May 10, 2002Date of Patent: August 5, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Katsuyoshi Mitsui
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Publication number: 20030080803Abstract: The boosting circuit provided in a semiconductor device includes a ring oscillator generating a pump clock having constant periods, a pump capacitor for performing a boost operation, and a pump capacitor input control unit provided between one electrode of the pump capacitor and the ring oscillator. The pump capacitor input control unit fixes one electrode of the pump capacitor to a prescribed voltage to apply stress of a desired level to the pump capacitor in response to a control signal that is activated at the time of burn-in test.Type: ApplicationFiled: October 26, 2001Publication date: May 1, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Yuichiro Komiya, Katsuyoshi Mitsui