Patents by Inventor Katsuyuki Fujita

Katsuyuki Fujita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190362659
    Abstract: An illuminating apparatus with a video projecting function suitable for a digital signage or the like, which has an excellent video displaying function and better usability for a user is provided. An illuminating apparatus includes: an illumination light source disposed in a housing and configured to generate illumination light; a video projecting apparatus disposed in the housing, the video projecting apparatus being configured to generate video light, the video light from the video projecting apparatus being projected into an illumination light area from the illumination light source; a motion detector configured to detect approach of a human body; and a controller configured to control an operation of at least one or both of the illumination light source and the video projecting apparatus on a basis of a detection signal from the motion detector, the controller being configured to adjust brightness of the illumination light from the illumination light source.
    Type: Application
    Filed: March 1, 2017
    Publication date: November 28, 2019
    Inventors: Katsuyuki WATANABE, Koji FUJITA, Nobuyuki KAKU
  • Patent number: 10410706
    Abstract: A memory includes a bit line connected to a memory cell and a read circuit to execute reading of data from the memory cell. The read circuit includes a first circuit having a first input terminal and detecting an output signal from the memory cell, a first transistor to control a current supplied to the memory cell based on a first control signal, and a second transistor. One terminal of the first transistor is connected to the first input terminal, the other terminal of the first transistor is connected to one terminal of the second transistor, the other terminal of the second transistor is connected to the bit line, and the one terminal and the other terminal of the first transistor are charged before data is read from the memory cell.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: September 10, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Akira Katayama, Katsuyuki Fujita
  • Patent number: 10403346
    Abstract: According to one embodiment, a semiconductor memory device comprises a first bank and a second bank. Each of the first bank and the second bank comprises a memory cell having a variable resistor element, a reference cell, a sense amplifier having a first input terminal electrically coupled to the memory cell and a second input terminal electrically coupled to the reference cell, and a first transistor electrically coupling the memory cell and the first input terminal of the sense amplifier. A gate of the first transistor of the first hank and a gate of the first transistor of the second bank are independently supplied with a voltage.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: September 3, 2019
    Assignees: TOSHIBA MEMORY CORPORATION, SK HYNIX INC.
    Inventors: Katsuyuki Fujita, Hyuck Sang Yim
  • Patent number: 10269404
    Abstract: A resistance change memory including a memory cell having a resistance change element; a reference voltage generating circuit which generates a reference adjustment voltage; a first transistor which has a source and a drain, the drain providing a reference current in accordance with the reference adjustment voltage; and a sense amplifier which compares a cell current flowing through the memory cell with the reference current flowing through the first transistor. The reference voltage generating circuit includes a second transistor having a gate coupled to a gate of the first transistor, the reference adjustment voltage changing in accordance with a temperature, and the first transistor is an n-channel MOS transistor, and operates in a linear region which changes in a current value in accordance with the reference adjustment voltage.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: April 23, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Katsuyuki Fujita
  • Publication number: 20180277171
    Abstract: A semiconductor memory device includes a power source pad, a first bank including a plurality of memory cells, a second bank including a plurality of memory cells, the first bank being sandwiched between the power source pad and the second bank, first power supply lines connected to the power source pad and supplying power to the first bank and not to the second bank, and second power supply lines connected to the power source pad, passing over the first bank, and supplying power to the second bank and not to the first bank.
    Type: Application
    Filed: March 1, 2018
    Publication date: September 27, 2018
    Inventors: Fumiyoshi MATSUOKA, Katsuyuki FUJITA
  • Publication number: 20180197592
    Abstract: According to one embodiment, a memory includes a bit line connected to a memory cell; and a read circuit to execute reading of data from the memory cell. The read circuit includes a first circuit having a first input terminal and detecting an output signal from the memory cell; a first transistor to control a current supplied to the memory cell based on a first control signal; and a second transistor. One terminal of the first transistor is connected to the first input terminal, the other terminal of the first transistor is connected to one terminal of the second transistor, the other terminal of the second transistor is connected to the bit line, and the one terminal and the other terminal of the first transistor are charged before data is read from the memory cell.
    Type: Application
    Filed: March 6, 2018
    Publication date: July 12, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Akira KATAYAMA, Katsuyuki FUJITA
  • Publication number: 20180182442
    Abstract: According to one embodiment, a semiconductor memory device comprises a first bank and a second bank. Each of the first bank and the second bank comprises a memory cell having a variable resistor element, a reference cell, a sense amplifier having a first input terminal electrically coupled to the memory cell and a second input terminal electrically coupled to the reference cell, and a first transistor electrically coupling the memory cell and the first input terminal of the sense amplifier. A gate of the first transistor of the first hank and a gate of the first transistor of the second bank are independently supplied with a voltage.
    Type: Application
    Filed: February 23, 2018
    Publication date: June 28, 2018
    Applicants: TOSHIBA MEMORY CORPORATION, SK HYNIX INC.
    Inventors: Katsuyuki FUJITA, Hyuck Sang YIM
  • Patent number: 9887237
    Abstract: According to an embodiment, a magnetic storage device includes a semiconductor region including a trench; a gate electrode disposed in the trench; an insulation film covering the gate electrode and provided in a manner to fill the trench; and a magnetoresistive effect element including at least a first ferromagnetic layer, a second ferromagnetic layer, and a non-magnetic layer provided between the first ferromagnetic layer and the second ferromagnetic layer, the non-magnetic layer in a side surface of the magnetoresistive effect element including the non-magnetic layer being provided on a top surface of the insulation film.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: February 6, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shintaro Sakai, Keisuke Nakatsuka, Hiroyuki Kanaya, Yoshinori Kumura, Katsuyuki Fujita
  • Publication number: 20180033475
    Abstract: A resistance change memory including a memory cell having a resistance change element; a reference voltage generating circuit which generates a reference adjustment voltage; a first transistor which has a source and a drain, the drain providing a reference current in accordance with the reference adjustment voltage; and a sense amplifier which compares a cell current flowing through the memory cell with the reference current flowing through the first transistor. The reference voltage generating circuit includes a second transistor having a gate coupled to a gate of the first transistor, the reference adjustment voltage changing in accordance with a temperature, and the first transistor is an n-channel MOS transistor, and operates in a linear region which changes in a current value in accordance with the reference adjustment voltage.
    Type: Application
    Filed: October 6, 2017
    Publication date: February 1, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Katsuyuki FUJITA
  • Patent number: 9858973
    Abstract: According to one embodiment, a variable change memory includes a bit line, a word line, a memory cell array, a resonance line, a clock generator, and a write driver. The bit line extends in a first direction. The word line extends in a second direction. The memory cell array includes blocks. The each block includes memory cells including a transistor and a variable resistive element. The resonance line connects to a bit line. The clock generator is arranged in the memory cell array and applies a voltage to the resonance line. The write driver supplies a write current to the bit line. The voltage oscillates at the predetermined period and the write current are supplied to the bit line.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: January 2, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shintaro Sakai, Masahiko Nakayama, Katsuyuki Fujita, Hiromi Noro
  • Patent number: 9799385
    Abstract: According to one embodiment, a resistance change memory includes a memory cell, a reference voltage generating circuit, a first transistor and a sense amplifier. The memory cell includes a resistance change element. The reference voltage generating circuit generates a reference adjustment voltage. The first transistor provides a reference current in accordance with the reference adjustment voltage. The sense amplifier compares a cell current flowing through the memory cell with the reference current flowing through the first transistor.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: October 24, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Katsuyuki Fujita
  • Patent number: 9747966
    Abstract: According to one embodiment, a semiconductor memory device includes a memory cell; a reference signal generation circuit; a sense amplifier; a first transistor configured to electrically couple the memory cell and a first input terminal of the sense amplifier; a second transistor configured to electrically couple the reference signal generation circuit and a second input terminal of the sense amplifier; a first control circuit configured to supply a voltage to gates of the first transistor and the second transistor; a second control circuit configured to supply a first voltage except 0V to a back gate of the first transistor; and a third control circuit configured to supply a second voltage except 0V to a back gate of the second transistor.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: August 29, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Katsuyuki Fujita
  • Publication number: 20170141157
    Abstract: According to an embodiment, a magnetic storage device includes a semiconductor region including a trench; a gate electrode disposed in the trench; an insulation film covering the gate electrode and provided in a manner to fill the trench; and a magnetoresistive effect element including at least a first ferromagnetic layer, a second ferromagnetic layer, and a non-magnetic layer provided between the first ferromagnetic layer and the second ferromagnetic layer, the non-magnetic layer in a side surface of the magnetoresistive effect element including the non-magnetic layer being provided on a top surface of the insulation film.
    Type: Application
    Filed: March 9, 2016
    Publication date: May 18, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shintaro SAKAI, Keisuke NAKATSUKA, Hiroyuki KANAYA, Yoshinori KUMURA, Katsuyuki FUJITA
  • Publication number: 20170076791
    Abstract: According to one embodiment, a semiconductor memory device includes: first and second memory cells each including a variable resistance element; a first sense amplifier having a first input terminal coupled to the first memory cell; a second sense amplifier having a first input terminal coupled to the second memory cell; and a first current generator including a first resistance element coupled to a second input terminal of the first sense amplifier and a second input terminal of the second sense amplifier, and generating a first current supplied to the first sense amplifier or the second sense amplifier. The first sense amplifier is set to an active state and the second sense amplifier is set to an inactive state in a read operation of the first memory cell.
    Type: Application
    Filed: March 9, 2016
    Publication date: March 16, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masahiro TAKAHASHI, Katsuyuki FUJITA
  • Patent number: 9589621
    Abstract: A resistance change memory includes a memory cell array comprising memory cells including magnetic tunnel junction (MTJ) elements; a write and read circuit which performs a write operation and a read operation for the memory cells; a temperature sensor which outputs temperature information corresponding to a temperature of the memory cell array; and a memory controller which controls the write operation and the read operation by the write and read circuit in response to the temperature information, such that a first time period from a write command input to a pre-charge command input is variable according to the temperature information, while a second time period from an active command input to the pre-charge command input is fixed constant regardless of the temperature information.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: March 7, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Katsuyuki Fujita
  • Publication number: 20170062033
    Abstract: According to one embodiment, a semiconductor memory device includes a memory cell; a reference signal generation circuit; a sense amplifier; a first transistor configured to electrically couple the memory cell and a first input terminal of the sense amplifier; a second transistor configured to electrically couple the reference signal generation circuit and a second input terminal of the sense amplifier; a first control circuit configured to supply a voltage to gates of the first transistor and the second transistor; a second control circuit configured to supply a first voltage except 0V to a back gate of the first transistor; and a third control circuit configured to supply a second voltage except 0V to a back gate of the second transistor.
    Type: Application
    Filed: March 9, 2016
    Publication date: March 2, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Katsuyuki FUJITA
  • Publication number: 20160379697
    Abstract: According to one embodiment, a variable change memory includes a bit line, a word line, a memory cell array, a resonance line, a clock generator, and a write driver. The bit line extends in a first direction. The word line extends in a second direction. The memory cell array includes blocks. The each block includes memory cells including a transistor and a variable resistive element. The resonance line connects to a bit line. The clock generator is arranged in the memory cell array and applies a voltage to the resonance line. The write driver supplies a write current to the bit line. The voltage oscillates at the predetermined period and the write current are supplied to the bit line.
    Type: Application
    Filed: September 9, 2016
    Publication date: December 29, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shintaro SAKAI, Masahiko NAKAYAMA, Katsuyuki FUJITA, Hiromi NORO
  • Patent number: 9502140
    Abstract: According to one embodiment, a semiconductor memory device includes first word lines connected to a memory cell array, second word lines connected to a redundancy area, a first row decoder configured to perform selecting from the first word lines based on a row address, a judgment circuit configured to determine whether or not a replacement operation with the redundancy area is needed based on a redundancy address included in the row address, and a second row decoder configured to perform selecting from the second word lines. The row address includes a first row address and a second row address input in order in a time-sharing method. The first row address includes all of the redundancy address.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: November 22, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Katsuyuki Fujita
  • Patent number: 9424906
    Abstract: A semiconductor storage device according to the present embodiment includes a plurality of memory units respectively comprising a plurality of memory cells. A data bus is shared by the memory units and transfers data from the memory units or to the memory units. A timing controller includes a delay time unit shared by the memory units sharing the data bus. The timing controller is configured to output a control signal for driving the memory units after a predetermined delay time elapses since receiving an input signal.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: August 23, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuyuki Fujita, Katsuhiko Hoya
  • Patent number: RE46920
    Abstract: According to one embodiment, a semiconductor memory device includes a variable resistance element configured to store data “0” and data “1” in accordance with a change in resistance value, a current generator configured to generate a reference current for determining data of the variable resistance element, and having an admittance middle at a level in between an admittance of a variable resistance element storing data “0” and an admittance of a variable resistance element storing data “1”, and a sense amplifier includes a first input terminal connected to the variable resistance element and a second input terminal connected to the current generator, and configured to compare currents of the first input terminal and the second input terminal.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: June 26, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Katsuyuki Fujita, Kenji Tsuchida