Patents by Inventor Katsuyuki Horita
Katsuyuki Horita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120208346Abstract: A polysilazane film is formed over the main surface of a semiconductor substrate in such a manner that the upper surface level of the polysilazane film buried in a trench of 0.2 ?m or less in width becomes higher than that of a pad insulating film and the upper surface level of the polysilazane film buried in a trench of 1.0 ?m or more in width becomes lower than that of the pad insulating film. Then, heat treatment is conducted at 300° C. or more to convert the polysilazane film into a first buried film made of silicon oxide (SiO2) and remove a void in the upper portion of the narrower trench.Type: ApplicationFiled: January 31, 2012Publication date: August 16, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Masaru KADOSHIMA, Hiroshi Umeda, Tatsunori Kaneoka, Katsuyuki Horita
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Publication number: 20120119309Abstract: There is provided a technology capable of providing desirable operation characteristics in a field effect transistor formed in an active region surrounded by a trench type element isolation part. An element isolation part includes trench type element isolation films, diffusion preventive films each including a silicon film or a silicon oxide film, and having a thickness of 10 to 20 nm formed over the top surfaces of the trench type element isolation films, and silicon oxide films each with a thickness of 0.5 to 2 nm formed over the top surfaces of the diffusion preventive films. The composition of the diffusion preventive film is SiOx (0?x<2). Each composition of the trench type element isolation films and the silicon oxide films is set to be SiO2.Type: ApplicationFiled: November 1, 2011Publication date: May 17, 2012Inventor: Katsuyuki HORITA
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Patent number: 8043918Abstract: To manufacture in high productivity a semiconductor device capable of securely achieving element isolation by a trench-type element isolation and capable of effectively preventing potentials of adjacent elements from affecting other nodes, a method of manufacturing the semiconductor device includes: a step of forming a first layer on a substrate; a step of forming a trench by etching the first layer and the substrate; a step of thermally oxidizing an inner wall of the trench; a step of depositing a first conductive film having a film thickness equal to or larger than one half of the trench width of the trench on the substrate including the trench; a step of removing a first conductive film from the first layer by a CMP method and keeping the first conductive film left in only the trench; a step of anisotropically etching the first conductive film within the trench to adjust the height of the conductive film to become lower than the height of the surface of the substrate; a step of depositing an insulating filType: GrantFiled: July 21, 2010Date of Patent: October 25, 2011Assignee: Renesas Electronics CorporationInventors: Takashi Kuroi, Katsuyuki Horita, Masashi Kitazawa, Masato Ishibashi
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Publication number: 20100283108Abstract: To provide a semiconductor device provided with an element isolation structure capable of hindering an adverse effect on electric characteristics of a semiconductor element, and a method of manufacturing the same. The thickness of a first silicon oxide film left in a shallow trench isolation having a relatively narrow width is thinner than the first silicon oxide film left in a shallow trench isolation having a relatively wide width. A second silicon oxide film (an upper layer) having a relatively high compressive stress by an HDP-CVD method is more thickly laminated over the first silicon oxide film in a lower layer by a thinned thickness of the first silicon oxide film. The compressive stress of an element isolation oxide film finally formed in a shallow trench isolation having a relatively narrow width is more enhanced.Type: ApplicationFiled: April 22, 2010Publication date: November 11, 2010Inventors: Mahito Sawada, Tatsunori Kaneoka, Katsuyuki Horita
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Publication number: 20100285651Abstract: To manufacture in high productivity a semiconductor device capable of securely achieving element isolation by a trench-type element isolation and capable of effectively preventing potentials of adjacent elements from affecting other nodes, a method of manufacturing the semiconductor device includes: a step of forming a first layer on a substrate; a step of forming a trench by etching the first layer and the substrate; a step of thermally oxidizing an inner wall of the trench; a step of depositing a first conductive film having a film thickness equal to or larger than one half of the trench width of the trench on the substrate including the trench; a step of removing a first conductive film from the first layer by a CMP method and keeping the first conductive film left in only the trench; a step of anisotropically etching the first conductive film within the trench to adjust the height of the conductive film to become lower than the height of the surface of the substrate; a step of depositing an insulating filType: ApplicationFiled: July 21, 2010Publication date: November 11, 2010Applicant: Renesas Technology Corp.Inventors: Takashi KUROI, Katsuyuki HORITA, Masashi KITAZAWA, Masato ISHIBASHI
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Patent number: 7791163Abstract: In the process of manufacturing a semiconductor device, a first layer is formed on a substrate, and the first layer and the substrate are etched to form a trench. The inner wall of the trench is thermally oxidized. On the substrate, including inside the trench, is deposited a first conductive film having a thickness equal to or larger than one half of the width of the trench. The first conductive film on the first layer is removed by chemical mechanical polishing such that the first conductive film remains in only the trench. The height of the first conductive film in the trench is adjusted to be lower than a surface of the substrate by anisotropically etching the first conductive film. An insulating film is deposited on the substrate by chemical vapor deposition to cover an upper surface of the first conductive film in the trench. The insulating film is flattened by chemical mechanical polishing, and the first layer is removed.Type: GrantFiled: October 18, 2005Date of Patent: September 7, 2010Assignee: Renesas Technology Corp.Inventors: Takashi Kuroi, Katsuyuki Horita, Masashi Kitazawa, Masato Ishibashi
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Publication number: 20100190306Abstract: A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film and a silicon nitride film being formed, p-type impurity ions are implanted in a Y direction from diagonally above. As for an implant angle ? of the ion implantation, an implant angle is adopted that satisfies the relationship tan?1 (W2/T)<??tan?1 (W1/T), where W1 is an interval between a first portion and a fourth portion and an interval between a third portion and a sixth portion; W2 is an interval between a second portion and a fifth portion; T is a total film thickness of the silicon oxide film and the silicon nitride film. When the implant angle ? is controlled within that range, impurity ions are implanted into a second side surface and a fifth side surface through a silicon oxide film.Type: ApplicationFiled: April 5, 2010Publication date: July 29, 2010Applicant: Renesas Technology Corp.Inventors: Yoshinori Tanaka, Katsuyuki Horita, Heiji Kobayashi
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Patent number: 7691713Abstract: A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film (20) and a silicon nitride film (21) being formed, p-type impurity ions (23.sub.1, 23.sub.2) are implanted in a Y direction from diagonally above. As for an implant angle .alpha. of the ion implantation, an implant angle is adopted that satisfies the relationship tan?1 (W2/T)<??tan?1 (W1/T), where W1 is an interval between a first portion (211) and a fourth portion (214) and an interval between a third portion (213) and a sixth portion (216); W2 is an interval between a second portion (212) and a fifth portion (215); T is a total film thickness of the silicon oxide film (20) and the silicon nitride film (21).Type: GrantFiled: June 25, 2007Date of Patent: April 6, 2010Assignee: Renesas Technology Corp.Inventors: Yoshinori Tanaka, Katsuyuki Horita, Heiji Kobayashi
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Publication number: 20100044802Abstract: Provided are a semiconductor device making it possible to form an element region having a dimension close to a designed dimension, restrain a phenomenon similar to gate-induced drain leakage, and further restrain compressive stress to be applied to the element region by oxidation of a conductive film; and a method for manufacturing the semiconductor device. Trenches are made in a main surface of a semiconductor substrate. By oxidizing the wall surface of each of the trenches, a first oxide film is formed on the wall surface. An embedded conductive film is formed to be embedded into the trench. The embedded conductive film is oxidized in an atmosphere containing an active oxidizing species, thereby forming a second oxide film. A third oxide film is formed on the second oxide film by CVD or coating method.Type: ApplicationFiled: June 30, 2009Publication date: February 25, 2010Inventors: Masato Ishibashi, Katsuyuki Horita, Tomohiro Yamashita, Takaaki Tsunomura, Takashi Kuroi
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Publication number: 20080113480Abstract: A semiconductor substrate is covered with a resist mask and then an opening for exposing a whole upper surface of a polysilicon gate is formed by photo lithography and dry etching. Thereafter, nitrogen ions are implanted into the polysilicon gate through the opening. Implantation energy at this time is set so that the implanted ions may not break through the polysilicon gate.Type: ApplicationFiled: November 14, 2007Publication date: May 15, 2008Applicant: Renesas Technology Corp.Inventors: Yukio NISHIDA, Takashi Hayashi, Tomohiro Yamashita, Katsuyuki Horita, Katsumi Eikyu
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Publication number: 20070243687Abstract: A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film (20) and a silicon nitride film (21) being formed, p-type impurity ions (23.sub.1, 23.sub.2) are implanted in a Y direction from diagonally above. As for an implant angle .alpha. of the ion implantation, an implant angle is adopted that satisfies the relationship tan?1 (W2/T)<??tan?1 (W1/T), where W1 is an interval between a first portion (211) and a fourth portion (214) and an interval between a third portion (213) and a sixth portion (216); W2 is an interval between a second portion (212) and a fifth portion (215); T is a total film thickness of the silicon oxide film (20) and the silicon nitride film (21).Type: ApplicationFiled: June 25, 2007Publication date: October 18, 2007Applicant: Renesas Technology Corp.Inventors: Yoshinori Tanaka, Katsuyuki Horita, Heiji Kobayashi
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Publication number: 20070241373Abstract: In the process of manufacturing a semiconductor device, a first layer is formed on a substrate, and the first layer and the substrate are etched to form a trench. The inner wall of the trench is thermally oxidized. On the substrate, including inside the trench, is deposited a first conductive film having a thickness equal to or larger than one half of the width of the trench. The first conductive film on the first layer is removed by chemical mechanical polishing such that the first conductive film remains in only the trench. The height of the first conductive film in the trench is adjusted to be lower than a surface of the substrate by anisotropically etching the first conductive film. An insulating film is deposited on the substrate by chemical vapor deposition to cover an upper surface of the first conductive film in the trench. The insulating film is flattened by chemical mechanical polishing, and the first layer is removed.Type: ApplicationFiled: October 18, 2005Publication date: October 18, 2007Applicant: Renesas Technology Corp.Inventors: Takashi Kuroi, Katsuyuki Horita, Masashi Kitazawa, Masato Ishibashi
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Patent number: 7244655Abstract: A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film (20) and a silicon nitride film (21) being formed, p-type impurity ions (231, 232) are implanted in a Y direction from diagonally above. As for an implant angle ? of the ion implantation, an implant angle is adopted that satisfies the relationship tan?1(W2/T)<??tan?1(W1/T), where W1 is an interval between a first portion (211) and a fourth portion (214) and an interval between a third portion (213) and a sixth portion (216); W2 is an interval between a second portion (212) and a fifth portion (215); T is a total film thickness of the silicon oxide film (20) and the silicon nitride film (21). When the implant angle ? is controlled within that range, impurity ions (231, 232) are implanted into a second side surface (10A2) and a fifth side surface (10A5) through a silicon oxide film (13).Type: GrantFiled: December 2, 2005Date of Patent: July 17, 2007Assignee: Renesas Technology Corp.Inventors: Yoshinori Tanaka, Katsuyuki Horita, Heiji Kobayashi
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Publication number: 20070138574Abstract: The top ends of polysilicon gate electrodes with different gate lengths are formed so as to be equally high and lower than the top end of the side wall. A metal film is formed so as to cover the polysilicon gate electrodes, followed by silicidation by thermal treatment. Since the top ends of the polysilicon gate electrodes are formed lower than the top end of the side wall, a silicon side reaction is not accelerated even in the case of a fine gate length, and proceeds in a one-dimensional manner. As a result, full-silicide gate electrodes having a uniform metal composition ratio can be stably formed even using the polysilicon gates with different gate lengths.Type: ApplicationFiled: November 27, 2006Publication date: June 21, 2007Applicant: Renesas Technology Corp.Inventors: Katsumi EIKYU, Tomohiro Yamashita, Katsuyuki Horita, Takashi Hayashi
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Publication number: 20060270121Abstract: Even if the insulated isolation structure which makes element isolation using partial and full isolation combined use technology is manufactured, the manufacturing method of a semiconductor device which can manufacture the semiconductor device with which characteristics good as a semiconductor element formed in the SOI layer where insulated isolation was made are obtained is obtained. Etching to an inner wall oxide film and an SOI layer is performed by using as a mask the resist and trench mask which were patterned, and the trench for full isolation which penetrates an SOI layer and reaches an embedded insulating layer is formed. Although a part of CVD oxide films with which the resist is not formed in the upper part are removed at this time, since a silicon nitride film is protected by the CVD oxide film, the thickness of a silicon nitride film is kept constant.Type: ApplicationFiled: May 4, 2006Publication date: November 30, 2006Applicant: Renesas Technology Corp.Inventors: Takashi Ipposhi, Katsuyuki Horita, Shigeto Maegawa
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Publication number: 20060214212Abstract: First active region and second and third active regions are defined in a semiconductor substrate within a memory cell area and a logic circuit area, respectively. First to third MOS transistors are formed in the first to third active regions, respectively. As viewed from above, the length of the first and second active regions along the gate width is not greater than the length of the third active region along the gate width. In the isolation insulation film, the upper surface of a peripheral portion provided around the first active region is positioned below the upper surface thereof, and the upper surface of a peripheral portion provided around the second active region is positioned below the upper surface thereof. A gate electrode is formed on the upper surfaces of the first to third active regions and the side surfaces of the first and second active regions.Type: ApplicationFiled: March 22, 2006Publication date: September 28, 2006Applicant: Renesas Technology Corp.Inventors: Katsuyuki HORITA, Masato ISHIBASHI
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Publication number: 20060079061Abstract: A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film (20) and a silicon nitride film (21) being formed, p-type impurity ions (231, 232) are implanted in a Y direction from diagonally above. As for an implant angle ? of the ion implantation, an implant angle is adopted that satisfies the relationship tan?1(W2/T)<??tan?1(W1/T), where W1 is an interval between a first portion (211) and a fourth portion (214) and an interval between a third portion (213) and a sixth portion (216); W2 is an interval between a second portion (212) and a fifth portion (215); T is a total film thickness of the silicon oxide film (20) and the silicon nitride film (21). When the implant angle ? is controlled within that range, impurity ions (231, 232) are implanted into a second side surface (10A2) and a fifth side surface (10A5) through a silicon oxide film (13).Type: ApplicationFiled: December 2, 2005Publication date: April 13, 2006Applicant: Renesas Technology Corp.Inventors: Yoshinori Tanaka, Katsuyuki Horita, Heiji Kobayashi
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Patent number: 6998319Abstract: A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film (20) and a silicon nitride film (21) being formed, p-type impurity ions (231, 232) are implanted in a Y direction from diagonally above. As for an implant angle ? of the ion implantation, an implant angle is adopted that satisfies the relationship tan?1(W2/T)<??tan?1(W1/T), where W1 is an interval between a first portion (211) and a fourth portion (214) and an interval between a third portion (213) and a sixth portion (216); W2 is an interval between a second portion (212) and a fifth portion (215); T is a total film thickness of the silicon oxide film (20) and the silicon nitride film (21). When the implant angle ? is controlled within that range, impurity ions (231, 232) are implanted into a second side surface (10A2) and a fifth side surface (10A5) through a silicon oxide film (13).Type: GrantFiled: December 9, 2003Date of Patent: February 14, 2006Assignee: Renesas Technology Corp.Inventors: Yoshinori Tanaka, Katsuyuki Horita, Heiji Kobayashi
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Publication number: 20060027883Abstract: An object is to obtain a semiconductor device in which channel length is reduced without increasing the gate resistance to realize higher operation speed and its manufacturing method.Type: ApplicationFiled: October 4, 2005Publication date: February 9, 2006Applicant: Renesas Technology Corp.Inventors: Takashi Kuroi, Yasuyoshi Itoh, Katsuyuki Horita, Katsuomi Shiozawa
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Patent number: 6890837Abstract: A substrate surface (10S) is thermally oxidized to form an oxide film. The oxide film is patterned so that the substrate surface (10S) in an active region is exposed. An oxide film (20) is thereby provided. An exposed substrate surface (10S) is thermally oxidized, to form a thermal oxide film. This thermal oxide film is thereafter removed at least in an element forming region. A silicon film (41) is epitaxially grown on the exposed substrate surface (10S). Thereafter the silicon film (41) is polished by CMP to an extent that an upper surface of the silicon film after polishing is not more than an upper surface of the oxide film (20) in height. Next, the surface of the silicon film is thermally oxidized to form a thermal oxide film. After ion implantation of various types, this thermal oxide film is removed.Type: GrantFiled: October 14, 2003Date of Patent: May 10, 2005Assignee: Renesas Technology Corp.Inventors: Takashi Kuroi, Katsuyuki Horita, Katsuomi Shiozawa