Patents by Inventor Katsuyuki Sekine

Katsuyuki Sekine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10367000
    Abstract: According to one embodiment, a semiconductor device includes a foundation layer, a stacked body provided above the foundation layer, a semiconductor body, and a charge storage portion. The stacked body includes a plurality of electrode layers stacked with an air gap interposed, a plurality of select gate layers stacked in a stacking direction of the electrode layers, and an insulating body provided between the select gate layers adjacent to each other in the stacking direction. The semiconductor body extends in the stacking direction in the stacked body. The charge storage portion is provided between the semiconductor body and one of the electrode layers.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: July 30, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Takashi Fukushima, Katsuyuki Sekine, Satoshi Nagashima, Hisataka Meguro
  • Patent number: 10269821
    Abstract: A semiconductor memory device includes first and second electrode films, an interlayer insulating film, a semiconductor pillar, and a first insulating film. The first electrode film extends in a first direction. The second electrode film is provided separately from the first electrode film in a second direction and extends in the first direction. The interlayer insulating film is provided between the first and the second electrode films. The first insulating film includes first and second insulating regions. A concentration of nitrogen in the first position of the second insulating region is higher than a concentration of nitrogen in the second position between the first position and the semiconductor pillar. A concentration of nitrogen in the first insulating region is lower than the concentration of the nitrogen in the first position.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: April 23, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masao Shingu, Katsuyuki Sekine, Hirokazu Ishigaki, Makoto Fujiwara
  • Patent number: 10263008
    Abstract: According to an embodiment, a semiconductor memory device comprises a plurality of control gate electrodes, a semiconductor layer, and a first insulating layer. The plurality of control gate electrodes are stacked above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The first insulating layer is positioned between the semiconductor layer and the control gate electrode. In addition, part of the first insulating layer is a charge accumulation layer. Moreover, part of the first insulating layer is an oxide layer positioned upwardly of the charge accumulation layer.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: April 16, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Daisuke Nishida, Katsuyuki Sekine, Hirokazu Ishigaki, Yasuhiro Shimura
  • Patent number: 10229924
    Abstract: A semiconductor memory device according to an embodiment includes first and second semiconductor pillars extending in a first direction and being arranged along a second direction, first and second interconnects extending in a third direction and being provided between the first semiconductor pillar and the second semiconductor pillar, a first electrode provided between the first semiconductor pillar and the first interconnect, a second electrode provided between the second semiconductor pillar and the second interconnect, third and fourth interconnects extending in the second direction, a first contact contacting the first semiconductor pillar and being connected to the third interconnect, and a second contact contacting the second semiconductor pillar and being connected to the fourth interconnect. The third and fourth interconnects each pass through both a region directly above the first semiconductor pillar and a region directly above the second semiconductor pillar.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: March 12, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Wataru Sakamoto, Tatsuya Kato, Yuta Watanabe, Katsuyuki Sekine, Toshiyuki Iwamoto, Fumitaka Arai
  • Publication number: 20190005433
    Abstract: The present invention includes: a first divider that divides time series data measured at a normal time into periodic data in period units; a reference data generator that generates reference data based on a plurality of pieces of periodic data; an allowable error calculator that calculates an allowable error of a divergence value, based on the time series data of the normal time and the reference data the divergence value indicates a degree of divergence from the reference data; a divergence value calculator that calculates a divergence value between time series data for detection, the time series data for detection is a detection object for detection of a non-normal state; and a detector that detects the non-normal state in accordance with whether or not the divergence value is within a range of allowable errors.
    Type: Application
    Filed: May 31, 2016
    Publication date: January 3, 2019
    Inventor: Katsuyuki SEKINE
  • Publication number: 20180277555
    Abstract: According to one embodiment, a semiconductor device includes a foundation layer, a stacked body provided above the foundation layer, a semiconductor body, and a charge storage portion. The stacked body includes a plurality of electrode layers stacked with an air gap interposed, a plurality of select gate layers stacked in a stacking direction of the electrode layers, and an insulating body provided between the select gate layers adjacent to each other in the stacking direction. The semiconductor body extends in the stacking direction in the stacked body. The charge storage portion is provided between the semiconductor body and one of the electrode layers.
    Type: Application
    Filed: September 8, 2017
    Publication date: September 27, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Takashi Fukushima, Katsuyuki Sekine, Satoshi Nagashima, Hisataka Meguro
  • Patent number: 9966381
    Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a first conductive film provided on a first region of the first insulating film, a second conductive film provided on a second region of the first insulating film, a first stacked body provided on the first conductive film, a second stacked body provided on the second conductive film, a first semiconductor pillar, and two conductive pillars. In the first stacked body, a second insulating film and an electrode film are stacked alternately. In the second stacked body, a third insulating film and a first film are stacked alternately. The two conductive pillars extend in the first direction through the second stacked body, are separated from the second conductive film, sandwich the second conductive film, and are connected at a bottom ends of the second conductive pillars to the semiconductor substrate.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: May 8, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Fumitaka Arai, Tatsuya Kato, Satoshi Nagashima, Katsuyuki Sekine, Yuta Watanabe, Keisuke Kikutani, Atsushi Murakoshi
  • Publication number: 20180006050
    Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, and a second insulating film provided between the first electrode and the second electrode. The second electrode includes a thin sheet portion disposed on the first electrode side, and a thick sheet portion disposed on the semiconductor pillar side. A length in the first direction of the thick sheet portion is longer than a length in the first direction of the thin sheet portion.
    Type: Application
    Filed: September 14, 2017
    Publication date: January 4, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Yuta Watanabe, Fumitaka Arai, Katsuyuki Sekine, Toshiyuki Iwamoto, Wataru Sakamoto, Tatsuya Kato
  • Publication number: 20170373082
    Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, a second insulating film provided between the first electrode and the second electrode and on two first-direction sides of the first electrode, and a conductive film provided between the second electrode and the second insulating film, the conductive film not contacting the first insulating film.
    Type: Application
    Filed: August 22, 2017
    Publication date: December 28, 2017
    Applicant: Toshiba Memory Corporation
    Inventors: Katsuyuki SEKINE, Tatsuya KATO, Fumitaka ARAI, Toshiyuki IWAMOTO, Yuta WATANABE, Wataru SAKAMOTO, Hiroshi ITOKAWA, Akio KANEKO
  • Patent number: 9847342
    Abstract: A semiconductor memory device includes a first structural body, a second structural body and interconnections. The first and the second structural bodies are separated in a first direction and extend in a second direction. The interconnections are provided between the first structural body and the second structural body, extend in the second direction, and are separated from each other along a third direction. The first and the second structural bodies each includes an insulating member, a column-shaped body and an insulating film. The insulating member and the column-shaped body are disposed in an alternating manner along the second direction and extend in the third direction. The insulating members of the first and second structural bodies make contact with the interconnections.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: December 19, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Nagashima, Katsumi Yamamoto, Kohei Sakaike, Tatsuya Kato, Keisuke Kikutani, Fumitaka Arai, Atsushi Murakoshi, Shunichi Takeuchi, Katsuyuki Sekine
  • Publication number: 20170352735
    Abstract: A semiconductor memory device according to an embodiment, includes a pair of first electrodes, a semiconductor pillar, an inter-pillar insulating member, a first insulating film, a second electrode, and a second insulating film. The pair of first electrodes are separated from each other, and extend in a first direction. The semiconductor pillar and the inter-pillar insulating member are arranged alternately along the first direction between the pair of first electrodes. The semiconductor pillar and the inter-pillar insulating member extend in a second direction crossing the first direction. The first insulating film is provided at a periphery of the semiconductor pillar. The second electrode is provided between the first insulating film and each electrode of the pair of first electrodes. The second electrode is not provided between the semiconductor pillar and the inter-pillar insulating member. The second insulating film is provided between the second electrode and the first electrode.
    Type: Application
    Filed: August 23, 2017
    Publication date: December 7, 2017
    Applicant: Toshiba Memory Corporation
    Inventors: Tatsuya Kato, Fumitaka Arai, Katsuyuki Sekine, Toshiyuke Iwamoto, Yuta Watanabe, Wataru Sakamoto
  • Publication number: 20170352672
    Abstract: A semiconductor memory device according to an embodiment includes first and second semiconductor pillars extending in a first direction and being arranged along a second direction, first and second interconnects extending in a third direction and being provided between the first semiconductor pillar and the second semiconductor pillar, a first electrode provided between the first semiconductor pillar and the first interconnect, a second electrode provided between the second semiconductor pillar and the second interconnect, third and fourth interconnects extending in the second direction, a first contact contacting the first semiconductor pillar and being connected to the third interconnect, and a second contact contacting the second semiconductor pillar and being connected to the fourth interconnect. The third and fourth interconnects each pass through both a region directly above the first semiconductor pillar and a region directly above the second semiconductor pillar.
    Type: Application
    Filed: August 25, 2017
    Publication date: December 7, 2017
    Applicant: Toshiba Memory Corporation
    Inventors: Wataru SAKAMOTO, Tatsuya KATO, Yuta WATANABE, Katsuyuki SEKINE, Toshiyuki IWAMOTO, Fumitaka ARAI
  • Publication number: 20170352671
    Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the first electrode and the second electrode and on two first-direction sides of the first electrode, a second insulating film provided between the second electrode and the first insulating film and on two first-direction sides of the second electrode, a third insulating film provided between the second electrode and the semiconductor pillar, and a conductive film provided inside a region interposed between the first insulating film and the second insulating film.
    Type: Application
    Filed: August 23, 2017
    Publication date: December 7, 2017
    Applicant: Toshiba Memory Corporation
    Inventors: Tatsuya Kato, Fumitaka Arai, Katsuyuki Sekine, Toshiyuki Iwamoto, Yuta Watanabe, Wataru Sakamoto, Hiroshi Itokawa
  • Patent number: 9786678
    Abstract: According to an embodiment, a nonvolatile semiconductor memory device comprises a plurality of conductive layers stacked in a first direction via an inter-layer insulating layer. In addition, the nonvolatile semiconductor memory device comprises: a semiconductor layer having the first direction as a longer direction; a tunnel insulating layer contacting a side surface of the semiconductor layer; a charge accumulation layer contacting a side surface of the tunnel insulating layer; and a block insulating layer contacting a portion facing the conductive layer, of a side surface of the charge accumulation layer. Moreover, the portion facing the conductive layer, of the charge accumulation layer is thinner compared to a portion facing the inter-layer insulating layer, of the charge accumulation layer.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: October 10, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Katsuyuki Sekine, Masaaki Higuchi, Masao Shingu, Hirokazu Ishigaki, Naoki Yasuda
  • Publication number: 20170271348
    Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a first conductive film provided on a first region of the first insulating film, a second conductive film provided on a second region of the first insulating film, a first stacked body provided on the first conductive film, a second stacked body provided on the second conductive film, a first semiconductor pillar, and two conductive pillars. In the first stacked body, a second insulating film and an electrode film are stacked alternately. In the second stacked body, a third insulating film and a first film are stacked alternately. The two conductive pillars extend in the first direction through the second stacked body, are separated from the second conductive film, sandwich the second conductive film, and are connected at a bottom ends of the second conductive pillars to the semiconductor substrate.
    Type: Application
    Filed: September 16, 2016
    Publication date: September 21, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Fumitaka ARAI, Tatsuya KATO, Satoshi NAGASHIMA, Katsuyuki SEKINE, Yuta WATANABE, Keisuke KIKUTANI, Atsushi MURAKOSHI
  • Publication number: 20170263619
    Abstract: A semiconductor memory device includes a first structural body, a second structural body and interconnections. The first and the second structural bodies are separated in a first direction and extend in a second direction. The interconnections are provided between the first structural body and the second structural body, extend in the second direction, and are separated from each other along a third direction. The first and the second structural bodies each includes an insulating member, a column-shaped body and an insulating film. The insulating member and the column-shaped body are disposed in an alternating manner along the second direction and extend in the third direction. The insulating members of the first and second structural bodies make contact with the interconnections.
    Type: Application
    Filed: September 16, 2016
    Publication date: September 14, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Satoshi NAGASHIMA, Katsumi YAMAMOTO, Kohei SAKAIKE, Tatsuya KATO, Keisuke KlKUTANI, Fumitaka ARAI, Atsushi MURAKOSHI, Shunichi TAKEUCHI, Katsuyuki SEKINE
  • Publication number: 20170263629
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a stacked body; a first columnar portion; a second columnar portion; and a plurality of first interconnects. The stacked body is provided on the substrate and includes a plurality of electrode layers separately stacked each other. A distance between the first columnar portion and one end of the plurality of electrode layers in the first direction is smaller than a distance between the second columnar portion and the other end of the plurality of electrode layers in the first direction. In the same electrode layer, a first width of a first charge storage film of the first columnar portion is smaller than a second width of a second charge storage film of the second columnar portion.
    Type: Application
    Filed: September 6, 2016
    Publication date: September 14, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Katsuyuki SEKINE
  • Patent number: 9761605
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a stacked body; a first columnar portion; a second columnar portion; and a plurality of first interconnects. The stacked body is provided on the substrate and includes a plurality of electrode layers separately stacked each other. A distance between the first columnar portion and one end of the plurality of electrode layers in the first direction is smaller than a distance between the second columnar portion and the other end of the plurality of electrode layers in the first direction. In the same electrode layer, a first width of a first charge storage film of the first columnar portion is smaller than a second width of a second charge storage film of the second columnar portion.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: September 12, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Katsuyuki Sekine
  • Patent number: 9754954
    Abstract: According to one embodiment, a non-volatile memory device includes a plurality of electrodes, at least one semiconductor layer, conductive layers, and first and second insulating films. The electrodes are arranged side by side in a first direction. The semiconductor layer extends into the electrodes in the first direction. The conductive layers are provided between each electrode and the semiconductor layer and separated from each other in the first direction. The first insulating film contacts the conductive layers, and extends in the first direction along the semiconductor layer between the conductive layers and the semiconductor layer. The second insulating film is provided between the first insulating film and the semiconductor layer. The first insulating film includes a first portion located between the conductive layers and the second insulating film, and a second portion located between the interlayer insulating film and the second insulating film.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: September 5, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masaaki Higuchi, Katsuyuki Sekine, Fumiki Aiso, Takuo Ohashi, Tatsuya Okamoto
  • Publication number: 20170243945
    Abstract: In a semiconductor memory device, first insulating films are arranged along a first direction and a second direction and extend in a third direction. Interconnect is disposed between the first insulating films in the first direction and extends in the third direction. Electrodes are disposed between the first insulating films in the first direction on a second direction side of the interconnect, and is arranged along the third direction. Second insulating film is disposed between the interconnect and the electrodes. Semiconductor members are arranged along the third direction between the first insulating films in the second direction and extend in the first direction. The electrode is disposed between the interconnect and the semiconductor members. Third insulating film is disposed between the electrodes and the semiconductor member and is thicker than the second insulating film.
    Type: Application
    Filed: September 13, 2016
    Publication date: August 24, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: KATSUYUKI SEKINE, TATSUYA KATO, FUMITAKA ARAI, TOSHIYUKI IWAMOTO, YUTA WATANABE, ATSUSHI MURAKOSHI