Patents by Inventor Katsuyuki Sekine

Katsuyuki Sekine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130234222
    Abstract: A semiconductor memory device includes a substrate, a structure body, a semiconductor layer, and a memory film. The memory film is provided between the semiconductor layer and the plurality of electrode films. The memory film includes a charge storage film, a block film, and a tunnel film. The block film is provided between the charge storage film and the plurality of electrode films. The tunnel film is provided between the charge storage film and the semiconductor layer. The tunnel film includes a first film containing silicon oxide, a second film containing silicon oxide, and a third film provided between the first film and the second film and containing silicon oxynitride. When a composition of the silicon oxynitride contained in the third film is expressed by a ratio x of silicon oxide and a ratio (1?x) of silicon nitride, 0.5?x<1 holdes.
    Type: Application
    Filed: August 30, 2012
    Publication date: September 12, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Naoki YASUDA, Masaaki Higuchi, Katsuyuki Sekine, Masao Shingu
  • Publication number: 20130235646
    Abstract: A memory cell array is configured as an arrangement of memory cells disposed at intersections of a plurality of first lines and a plurality of second lines formed so as to intersect one another, each of the memory cells comprising a variable resistance element. A control circuit selectively drives the first lines and the second lines. The variable resistance element is configured by a transition metal oxide film. An electrode connected to the variable resistance element includes a polysilicon electrode configured from polysilicon. A block layer is formed between the polysilicon electrode and the variable resistance element.
    Type: Application
    Filed: August 31, 2012
    Publication date: September 12, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yasuhiro NOJIRI, Hiroyuki Fukumizu, Katsuyuki Sekine, Yutaka Ishibashi
  • Patent number: 8530876
    Abstract: According to one embodiment, a semiconductor memory device comprises a substrate, a lower electrode, a variable resistance film, and an upper electrode. The lower electrode is on the substrate. The variable resistance film is on the lower electrode and stores data. The upper electrode is on the variable resistance film. The variable resistance film comprises a first film, and a second film. The first film is on a side of at least one of the upper electrode and the lower electrode and contains a metal. The second film is between the first film and the other electrode and contains the metal and oxygen. A composition ratio [O]/[Me] of oxygen to the metal in the second film is lower than a stoichiometric ratio and higher than the composition ratio [O]/[Me] in the first film. The composition ratio [0]/[Me] changes between the first film and the second film.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: September 10, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kensuke Takano, Katsuyuki Sekine, Yoshio Ozawa
  • Publication number: 20130228737
    Abstract: According to an embodiment, a nonvolatile semiconductor memory device comprises memory cells in each of which are series-connected: a variable resistance element including a metal oxide; an electrode including a polysilicon layer and a SiGe layer formed between the polysilicon layer and the metal oxide; and a bipolar type current rectifying element.
    Type: Application
    Filed: August 31, 2012
    Publication date: September 5, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki FUKUMIZU, Yasuhiro Nojiri, Katsuyuki Sekine
  • Patent number: 8450715
    Abstract: According to one embodiment, a nonvolatile memory device includes a plurality of nonvolatile memory elements each of that includes a resistance change film. The resistance change film is capable of recording information by transitioning between a plurality of states having different resistances in response to at least one of a voltage applied to the resistance change film or a current passed through the resistance change film, and the resistance change film includes an oxide containing at least one element selected from the group consisting of Hf, Zr, Ni, Ta, W, Co, Al, Fe, Mn, Cr, and Nb. An impurity element contained in the resistance change film is at least one element selected from the group consisting of Mg, Ca, Sr, Ba, Sc, Y, La, V, Ta, B, Ga, In, Tl, C, Si, Ge, Sn, Pb, N, P, As, Sb, Bi, S, Se, and Te, and the impurity element has an absolute value of standard Gibbs energy of oxide formation larger than an absolute value of standard Gibbs energy of oxide formation of the element contained in the oxide.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: May 28, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kensuke Takano, Katsuyuki Sekine, Yoshio Ozawa, Ryota Fujitsuka, Mitsuru Sato
  • Patent number: 8411486
    Abstract: According to one embodiment, there is provided a method of manufacturing a nonvolatile memory device. In this method, a first voltage may be applied to a variable resistive element having a resistance value which is electrically rewritable in a high resistance and in a low resistance. In this method, a second voltage may be applied to the variable resistive element in a case where the resistance value of the variable resistive element to which the first voltage has been applied is greater than a resistance value of the low resistance and is not greater than a resistance value of the high resistance. Further, in this method, the applying of the second voltage to the variable resistive element may be repeated until the resistance value of the variable resistive element to which the second voltage has been applied falls within a range of the resistance value of the low resistance.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: April 2, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuyuki Sekine, Ryota Fujitsuka, Yoshio Ozawa
  • Patent number: 8389968
    Abstract: According to one embodiment, a nonvolatile memory device comprises a plurality of first lines, a plurality of second lines, and memory cells. Each of the memory cells comprise a variable resistor, and a diode. The variable resistor includes a first metal oxide film and is configured to reversibly change resistance value by energy application. The diode includes a second metal oxide film and is connected in series to the variable resistor. The first metal oxide film has at least one of dielectric constant lower than that of the second metal oxide film and physical film thickness greater than that of the second metal oxide film.
    Type: Grant
    Filed: June 7, 2010
    Date of Patent: March 5, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuyuki Sekine, Yoshio Ozawa
  • Patent number: 8373222
    Abstract: In a nonvolatile semiconductor memory device, a stacked body is provided on a silicon substrate by alternately stacking pluralities of isolation dielectric films and electrode films, a through-hole is formed in the stacked body to extend in the stacking direction, a memory film is formed by stacking a block layer, a charge layer and a tunnel layer in this order at an inner face of the through-hole, and thereby a silicon pillar is buried in the through-hole. At this time, the electrode film is protruded further than the isolation dielectric film toward the silicon pillar at the inner face of the through-hole, and an end face of the isolation dielectric film has a curved shape displacing toward the silicon pillar side as the electrode film is approached.
    Type: Grant
    Filed: August 19, 2009
    Date of Patent: February 12, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuyuki Sekine, Yoshio Ozawa
  • Patent number: 8299571
    Abstract: According to one embodiment, a resistance-change memory cell array in which a plurality of horizontal electrodes extending horizontally and a plurality of vertical electrodes extending vertically are arranged to configure a cross-point structure includes rectifying insulating films formed in contact with side surfaces of the vertical electrodes in facing regions between the horizontal electrodes and the vertical electrodes, variable resistance films formed in contact with side surfaces of the horizontal electrodes in the facing regions between the horizontal electrodes and the vertical electrodes, and conductive layers formed between the rectifying insulating films and the variable resistance films.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: October 30, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshio Ozawa, Katsuyuki Sekine
  • Patent number: 8278697
    Abstract: A semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, the second insulating film including a lower silicon nitride film, a lower silicon oxide film formed on the lower silicon nitride film, an intermediate insulating film formed on the lower silicon oxide film and containing a metal element, the intermediate insulating film having a relative dielectric constant of greater than 7, an upper silicon oxide film formed on the intermediate insulating film, and an upper silicon nitride film formed on the upper silicon oxide film.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: October 2, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Daisuke Nishida, Ryota Fujitsuka, Katsuyuki Sekine, Akihito Yamamoto, Katsuaki Natori, Yoshio Ozawa
  • Publication number: 20120235220
    Abstract: According to one embodiment, a semiconductor device includes a substrate, a stacked body, a first insulating film, a charge storage film, a second insulating film and a channel body. The stacked body includes a plurality of electrode layers and insulating layers which are alternately stacked above the substrate. The first insulating film is provided on a side wall of a hole which is formed through the stacked body. The charge storage film is provided on an inner side of the first insulating film. The charge storage film includes a protrusion part which protrudes toward the electrode layer with facing the electrode layer and has a film thickness thicker than a film thickness of a part other than the protrusion part. The second insulating film is provided on an inner side of the charge storage film. The channel body is provided on an inner side of the second insulating film.
    Type: Application
    Filed: September 16, 2011
    Publication date: September 20, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Katsuyuki SEKINE, Masaaki HIGUCHI
  • Publication number: 20120217461
    Abstract: A semiconductor memory device according to an embodiment includes: first lines provided on a substrate; second lines provided between the first lines and the substrate so as to intersect the first lines; and a first memory cell array including first memory cells, each of the first memory cells being provided at respective intersections of the first lines and the second lines and including a current rectifying element and a variable resistor connected in series. The variable resistor of the first memory cell includes a first recording layer and a second recording layer, the first recording layer being made of an oxide of a first metal material, the second recording layer being made of the first metal material and being formed so as to contact with the first recording layer. The second recording layer is closer to the first line than the first recording layer is.
    Type: Application
    Filed: February 24, 2012
    Publication date: August 30, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shigeki KOBAYASHI, Takashi Shigeoka, Mitsuru Sato, Takahiro Hirai, Katsuyuki Sekine, Kazuya Kinoshita, Soichi Yamazaki, Ryota Fujitsuka, Kensuke Takahashi, Yasuhiro Nojiri, Masaki Yamato, Hiroyuki Fukumizu, Takeshi Yamaguchi
  • Patent number: 8253189
    Abstract: A semiconductor device includes a semiconductor region, a tunnel insulating film formed on a surface of the semiconductor region, a charge-storage insulating film formed on a surface of the tunnel insulating film and containing silicon and nitrogen, a block insulating film formed on a surface of the charge-storage insulating film, and a control gate electrode formed on a surface of the block insulating film, wherein the tunnel insulating film has a first insulating film formed on the surface of the semiconductor region and containing silicon and oxygen, a second insulating film formed on a surface of the first insulating film, and a third insulating film formed on a surface of the second insulating film and containing silicon and oxygen, and a charge trap state in the second insulating film has a lower density than that in the charge-storage insulating film.
    Type: Grant
    Filed: July 28, 2009
    Date of Patent: August 28, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuyuki Sekine, Akiko Sekihara, Kensuke Takano, Yoshio Ozawa
  • Publication number: 20120187469
    Abstract: According to one embodiment, there is provided a method of manufacturing a semiconductor storage device. In the method, any one of Ge, Sn, C, and N is introduced as impurity to a surface of a semiconductor substrate. In the method, the semiconductor substrate is thermally oxidized so that a tunnel insulating film is formed on the surface of the semiconductor substrate to which the impurity is introduced. In the method, a gate having a charge accumulation layer is formed on the tunnel insulating film. In the method, impurity diffusion regions are formed in the semiconductor substrate in a self-aligned manner using the gate.
    Type: Application
    Filed: September 21, 2011
    Publication date: July 26, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Katsuyuki SEKINE, Junya FUJITA
  • Patent number: 8187973
    Abstract: A method for manufacturing a semiconductor device which includes: alternately supplying a silicon source and an oxidant to deposit a silicon oxide film on a surface of a semiconductor substrate, wherein the silicon source is supplied under a supply condition where an adsorption amount of molecules of the silicon source on the semiconductor substrate is increased without causing an adsorption saturation of the molecules of the silicon source on the semiconductor substrate, and wherein the oxidant is supplied under a supply condition where impurities remain in the molecules of the silicon source adsorbed on the semiconductor substrate.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: May 29, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuyuki Sekine, Kazuhei Yoshinaga
  • Publication number: 20120112263
    Abstract: A semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, the second insulating film including a lower silicon nitride film, a lower silicon oxide film formed on the lower silicon nitride film, an intermediate insulating film formed on the lower silicon oxide film and containing a metal element, the intermediate insulating film having a relative dielectric constant of greater than 7, an upper silicon oxide film formed on the intermediate insulating film, and an upper silicon nitride film formed on the upper silicon oxide film.
    Type: Application
    Filed: January 17, 2012
    Publication date: May 10, 2012
    Inventors: Masayuki Tanaka, Daikuse Nishida, Ryota Fujitsuka, Katsuyuki Sekine, Akihito Yamamoto, Katsuaki Natori, Yoshio Ozawa
  • Publication number: 20120068144
    Abstract: According to one embodiment, there are provided a first electrode, a second electrode, first and second variable-resistance layers that are arranged between the first electrode and the second electrode, and at least one non variable-resistance layer that is arranged so that positions of the first and second variable-resistance layers between the first electrode and the second electrode are symmetrical to each other.
    Type: Application
    Filed: April 29, 2011
    Publication date: March 22, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Ryota FUJITSUKA, Masahiro KIYOTOSHI, Katsuyuki SEKINE, Mitsuru SATO
  • Patent number: 8115249
    Abstract: In a nonvolatile semiconductor memory device, a tunnel insulating layer, a charge storage layer and a charge block layer are formed on a silicon substrate in this order, and a plurality of control gate electrodes are provided above the charge block layer. Moreover, a cap layer made of silicon nitride is formed between the charge block layer and each of the control gate electrode, the cap layer being divided for each gate control electrode.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: February 14, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Isao Kamioka, Yoshio Ozawa, Katsuyuki Sekine
  • Publication number: 20120034754
    Abstract: A semiconductor device manufacturing method has forming element isolation trenches in a semiconductor substrate, forming a silicon compound film in insides of the element isolation trenches in order to embed the element isolation trenches, conducting a first oxidation processing at a first temperature to reform a surface of the silicon compound film to a volatile matter emission preventing layer which permits passage of an oxidizing agent and impurities and which does not permit passage of a volatile matter containing silicon atoms, and conducting a second oxidation processing at a second temperature which is higher than the first temperature to form a coated silicon oxide film inside the element isolation trenches.
    Type: Application
    Filed: October 13, 2011
    Publication date: February 9, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazuaki Iwasawa, Takeshi Hoshi, Keisuke Nakazawa, Shogo Matsuo, Takashi Nakao, Ryu Kato, Tetsuya Kai, Katsuyuki Sekine
  • Patent number: 8110865
    Abstract: A semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, the second insulating film including a lower silicon nitride film, a lower silicon oxide film formed on the lower silicon nitride film, an intermediate insulating film formed on the lower silicon oxide film and containing a metal element, the intermediate insulating film having a relative dielectric constant of greater than 7, an upper silicon oxide film formed on the intermediate insulating film, and an upper silicon nitride film formed on the upper silicon oxide film.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: February 7, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Daisuke Nishida, Ryota Fujitsuka, Katsuyuki Sekine, Akihito Yamamoto, Katsuaki Natori, Yoshio Ozawa