Patents by Inventor Kauser Yakub JOHAR

Kauser Yakub JOHAR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11360850
    Abstract: An error protection key generation method and system are provided, the method being used to generate a key for use in computing an error protection code for an input data value according to a chosen error protection scheme. The method comprises inputting a plurality of desired data value sizes, and then applying a key generation algorithm to generate a key for use in computing the error protection code for a maximum data value size amongst the plurality of data value sizes. The key generation algorithm is arranged so that it generates the key so as to comprise a plurality of sub-keys, where each sub-key is associated with one of the input data value sizes, and where each sub-key conforms to a key requirement of the error protection scheme. As a result, a generic key is produced containing a plurality of sub-keys, where each sub-key is associated with a particular desired data value size, and can be extracted and used independently given that each sub-key conforms to the error protection scheme requirements.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: June 14, 2022
    Assignee: Arm Limited
    Inventors: Michele Riga, Kauser Yakub Johar
  • Patent number: 11221899
    Abstract: An apparatus is described comprising a cluster of processing elements. The cluster having a split mode in which the processing elements are configured to process independent processing workloads, and a lock mode in which the processing elements comprise at least one primary processing element and at least one redundant processing element, each redundant processing element configured to perform a redundant processing workload for checking correctness of a primary processing workload performed by the primary processing element. Each processing element has an associated local memory comprising a plurality of memory locations. A local memory access control mechanism is configured, during the lock mode, to allow the at least one primary processing element to access memory locations within the local memory associated with the at least one redundant processing element.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: January 11, 2022
    Assignee: Arm Limited
    Inventors: Kauser Yakub Johar, Loïc Pierron
  • Publication number: 20210089323
    Abstract: A processing system 2 includes a processing pipeline 12, 14, 16, 18, 28 which includes fetch circuitry 12 for fetching instructions to be executed from a memory 6, 8. Buffer control circuitry 34 is responsive to a programmable trigger, such as explicit hint instructions delimiting an instruction burst, or predetermined configuration data specifying parameters of a burst together with a synchronising instruction, to trigger the buffer control circuitry to stall a stallable portion of the processing pipeline (e.g. issue circuitry 16), to accumulate within one or more buffers 30, 32 fetched instructions starting from a predetermined starting instruction, and, when those instructions have been accumulated, to restart the stallable portion of the pipeline.
    Type: Application
    Filed: November 18, 2020
    Publication date: March 25, 2021
    Inventors: Jatin BHARTIA, Kauser Yakub JOHAR, Antony John Penton
  • Publication number: 20210089381
    Abstract: An apparatus is described comprising a cluster of processing elements. The cluster having a split mode in which the processing elements are configured to process independent processing workloads, and a lock mode in which the processing elements comprise at least one primary processing element and at least one redundant processing element, each redundant processing element configured to perform a redundant processing workload for checking correctness of a primary processing workload performed by the primary processing element. Each processing element has an associated local memory comprising a plurality of memory locations.
    Type: Application
    Filed: September 24, 2019
    Publication date: March 25, 2021
    Inventors: Kauser Yakub JOHAR, Loïc PIERRON
  • Patent number: 10896111
    Abstract: Circuitry comprises data handling circuitry having a memory, the data handling circuitry being operable in a primary mode in which the data handling circuitry performs a data handling function by accessing the memory and in a secondary mode in which the data handling circuitry performs the data handling function independently of the memory; test circuitry to control a test operation during execution of a set of data processing instructions by a data processor configured to execute data processing instructions by reference to the data handling function performed by the data handling circuitry; in which: the test circuitry is configured to control the data handling circuitry to transition from the primary mode to the secondary mode in response to initiation of a test operation on the memory so that the data processor executes one or more of the set of data processing instructions by reference to the data handling function performed by the data handling circuitry in the secondary mode at least while the test ope
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: January 19, 2021
    Assignee: Arm Limited
    Inventors: Mohammadi Shabbirhussain Bharmal, Kauser Yakub Johar, Francisco João Feliciano Gaspar
  • Patent number: 10866810
    Abstract: A processing system includes a processing pipeline which includes fetch circuitry for fetching instructions to be executed from a memory. Buffer control circuitry is responsive to a programmable trigger, such as explicit hint instructions delimiting an instruction burst, or predetermined configuration data specifying parameters of a burst together with a synchronising instruction, to trigger the buffer control circuitry to stall a stallable portion of the processing pipeline (e.g. issue circuitry), to accumulate within one or more buffers fetched instructions starting from a predetermined starting instruction, and, when those instructions have been accumulated, to restart the stallable portion of the pipeline.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: December 15, 2020
    Assignee: ARM LIMITED
    Inventors: Jatin Bhartia, Kauser Yakub Johar, Antony John Penton
  • Publication number: 20200201732
    Abstract: Circuitry comprises data handling circuitry having a memory, the data handling circuitry being operable in a primary mode in which the data handling circuitry performs a data handling function by accessing the memory and in a secondary mode in which the data handling circuitry performs the data handling function independently of the memory; test circuitry to control a test operation during execution of a set of data processing instructions by a data processor configured to execute data processing instructions by reference to the data handling function performed by the data handling circuitry; in which: the test circuitry is configured to control the data handling circuitry to transition from the primary mode to the secondary mode in response to initiation of a test operation on the memory so that the data processor executes one or more of the set of data processing instructions by reference to the data handling function performed by the data handling circuitry in the secondary mode at least while the test ope
    Type: Application
    Filed: October 31, 2019
    Publication date: June 25, 2020
    Inventors: Mohammadi Shabbirhussain BHARMAL, Kauser Yakub JOHAR, Francisco João Feliciano GASPAR
  • Patent number: 10620953
    Abstract: A data processing apparatus has prefetch circuitry for prefetching instructions from a data store into an instruction queue. Branch prediction circuitry is provided for predicting outcomes of branch instructions and the prefetch circuitry may prefetch instructions subsequent to the branch based on the predicted outcome. Instruction identifying circuitry identifies whether a given instruction prefetched from the data store is a predetermined type of program flow altering instruction and if so then controls the prefetch circuitry to halt prefetching of subsequent instructions into the instruction queue.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: April 14, 2020
    Assignee: ARM Limited
    Inventors: Kauser Yakub Johar, Antony John Penton
  • Patent number: 10503512
    Abstract: Apparatus for data processing and a method of data processing are provided, according to which the processing circuitry of the apparatus can access a memory system and execute data processing instructions in one context of multiple contexts which it supports. When the processing circuitry executes a barrier instruction, the resulting access ordering constraint may be limited to being enforced for accesses which have been initiated by the processing circuitry when operating in an identified context, which may for example be the context in which the barrier instruction has been executed. This provides a separation between the operation of the processing circuitry in its multiple possible contexts and in particular avoids delays in the completion of the access ordering constraint, for example relating to accesses to high latency regions of memory, from affecting the timing sensitivities of other contexts.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: December 10, 2019
    Assignee: ARM Limited
    Inventors: Simon John Craske, Alexander Alfred Hornung, Max John Batley, Kauser Yakub Johar
  • Patent number: 10331531
    Abstract: Apparatus and a method for processor core self-testing are disclosed. The apparatus comprises processor core circuitry to perform data processing operations by executing data processing instructions. Separate self-test control circuitry causes the processor core circuitry to temporarily switch from a first state of executing the data processing instructions to a second state of executing a self-test sequence of instructions, before returning to the first state of executing the data processing instructions without a reboot of the processor core circuitry being required. There is also self-test support circuitry, wherein the processor core circuitry is responsive to the self-test sequence of instructions to cause an export of at least one self-test data item via the self-test support circuitry to the self-test control circuitry.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: June 25, 2019
    Assignee: ARM Limited
    Inventors: Balaji Venu, Kauser Yakub Johar, Marco Bonino
  • Publication number: 20180357065
    Abstract: A processing system 2 includes a processing pipeline 12, 14, 16, 18, 28 which includes fetch circuitry 12 for fetching instructions to be executed from a memory 6, 8. Buffer control circuitry 34 is responsive to a programmable trigger, such as explicit hint instructions delimiting an instruction burst, or predetermined configuration data specifying parameters of a burst together with a synchronising instruction, to trigger the buffer control circuitry to stall a stallable portion of the processing pipeline (e.g. issue circuitry 16), to accumulate within one or more buffers 30, 32 fetched instructions starting from a predetermined starting instruction, and, when those instructions have been accumulated, to restart the stallable portion of the pipeline.
    Type: Application
    Filed: May 9, 2018
    Publication date: December 13, 2018
    Inventors: Jatin BHARTIA, Kauser Yakub JOHAR, Antony John Penton
  • Patent number: 10084478
    Abstract: An apparatus and method are provided for generating an error code for a block comprising a plurality of data bits and a plurality of address bits. The apparatus has block generation circuitry to generate a block comprising a plurality of data bits and a plurality of address bits, and error code generation circuitry for receiving that block and a mask array comprising a plurality of mask rows, and for then applying an error code generation algorithm to generate an error code for the block. The error code comprises a plurality of check bits, where each check bit is determined using the block and a corresponding mask row of the mask array. Each mask row comprises a plurality of mask bits, each mask bit being associated with a corresponding bit of the block.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: September 25, 2018
    Assignee: ARM Limited
    Inventor: Kauser Yakub Johar
  • Publication number: 20170346504
    Abstract: An apparatus and method are provided for generating an error code for a block comprising a plurality of data bits and a plurality of address bits. The apparatus has block generation circuitry to generate a block comprising a plurality of data bits and a plurality of address bits, and error code generation circuitry for receiving that block and a mask array comprising a plurality of mask rows, and for then applying an error code generation algorithm to generate an error code for the block. The error code comprises a plurality of check bits, where each check bit is determined using the block and a corresponding mask row of the mask array. Each mask row comprises a plurality of mask bits, each mask bit being associated with a corresponding bit of the block.
    Type: Application
    Filed: May 5, 2017
    Publication date: November 30, 2017
    Inventor: Kauser Yakub JOHAR
  • Publication number: 20170293541
    Abstract: Apparatus and a method for processor core self-testing are disclosed. The apparatus comprises processor core circuitry to perform data processing operations by executing data processing instructions. Separate self-test control circuitry causes the processor core circuitry to temporarily switch from a first state of executing the data processing instructions to a second state of executing a self-test sequence of instructions, before returning to the first state of executing the data processing instructions without a reboot of the processor core circuitry being required. There is also self-test support circuitry, wherein the processor core circuitry is responsive to the self-test sequence of instructions to cause an export of at least one self-test data item via the self-test support circuitry to the self-test control circuitry.
    Type: Application
    Filed: March 2, 2017
    Publication date: October 12, 2017
    Inventors: Balaji VENU, Kauser Yakub JOHAR, Marco BONINO
  • Publication number: 20170286116
    Abstract: A data processing apparatus has prefetch circuitry for prefetching instructions from a data store into an instruction queue. Branch prediction circuitry is provided for predicting outcomes of branch instructions and the prefetch circuitry may prefetch instructions subsequent to the branch based on the predicted outcome. Instruction identifying circuitry identifies whether a given instruction prefetched from the data store is a predetermined type of program flow altering instruction and if so then controls the prefetch circuitry to halt prefetching of subsequent instructions into the instruction queue.
    Type: Application
    Filed: February 14, 2017
    Publication date: October 5, 2017
    Inventors: Kauser Yakub JOHAR, Antony John PENTON
  • Publication number: 20160321137
    Abstract: An error protection key generation method and system are provided, the method being used to generate a key for use in computing an error protection code for an input data value according to a chosen error protection scheme. The method comprises inputting a plurality of desired data value sizes, and then applying a key generation algorithm to generate a key for use in computing the error protection code for a maximum data value size amongst the plurality of data value sizes. The key generation algorithm is arranged so that it generates the key so as to comprise a plurality of sub-keys, where each sub-key is associated with one of the input data value sizes, and where each sub-key conforms to a key requirement of the error protection scheme. As a result, a generic key is produced containing a plurality of sub-keys, where each sub-key is associated with a particular desired data value size, and can be extracted and used independently given that each sub-key conforms to the error protection scheme requirements.
    Type: Application
    Filed: March 18, 2016
    Publication date: November 3, 2016
    Inventors: Michele RIGA, Kauser Yakub JOHAR
  • Publication number: 20160139922
    Abstract: Apparatus for data processing and a method of data processing are provided, according to which the processing circuitry of the apparatus can access a memory system and execute data processing instructions in one context of multiple contexts which it supports. When the processing circuitry executes a barrier instruction, the resulting access ordering constraint may be limited to being enforced for accesses which have been initiated by the processing circuitry when operating in an identified context, which may for example be the context in which the barrier instruction has been executed. This provides a separation between the operation of the processing circuitry in its multiple possible contexts and in particular avoids delays in the completion of the access ordering constraint, for example relating to accesses to high latency regions of memory, from affecting the timing sensitivities of other contexts.
    Type: Application
    Filed: November 3, 2015
    Publication date: May 19, 2016
    Inventors: Simon John CRASKE, Alexander Alfred Hornung, Max John BATLEY, Kauser Yakub JOHAR