Patents by Inventor Kaushik Mazumdar
Kaushik Mazumdar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11960340Abstract: A method for controlling a data processing system includes detecting a droop in a power supply voltage of a functional circuit of the data processing system greater than a programmable droop threshold. An operation of the data processing system is throttled according to a programmable step size, a programmable assertion time, and a programmable de-assertion time in response to detecting the droop.Type: GrantFiled: November 8, 2021Date of Patent: April 16, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Eric J. Chapman, Stephen Victor Kosonocky, Kaushik Mazumdar, Vydhyanathan Kalyanasundharam, Samuel Naffziger, Eric M. Scott
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Publication number: 20240106438Abstract: An integrated circuit includes a power supply monitor, a clock generator, and a divider. The power supply monitor is operable to provide a trigger signal in response to a power supply voltage dropping below a threshold voltage. The clock generator is operable to provide a first clock signal having a frequency dependent on a value of a frequency control word, and to change the frequency of the first clock signal over time using a native slope in response to a change in the frequency control word. The divider is responsive to an assertion of the trigger signal to divide a frequency of the first clock signal by a divide value to provide a second clock signal.Type: ApplicationFiled: November 30, 2023Publication date: March 28, 2024Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Kaushik Mazumdar, Ashish Jain, Joyce Cheuk Wai Wong, Mikhail Rodionov
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Patent number: 11942953Abstract: A apparatus includes a reference signal generator, a droop detection circuit, a digital frequency-locked loop (DFLL), and a DFLL control circuit. The reference signal generator that receives a digital value and produces a pulse-density modulated signal based on the digital value. The droop detection circuit converts the pulse-density modulated signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop of the monitored supply voltage below a designated value relative to the analog signal, produces a droop detection signal. The DFLL provides a clock signal for synchronizing circuitry within a domain of the monitored supply voltage. The DFLL control circuit, responsive to receiving the droop detection signal, causes the DFLL to slow the clock signal.Type: GrantFiled: December 21, 2021Date of Patent: March 26, 2024Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Kaushik Mazumdar, Joyce Cheuk Wai Wong, Naeem Ibrahim Ally, Stephen Victor Kosonocky
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Patent number: 11921529Abstract: Described is an apparatus which comprises: a plurality of transistors coupled to an input power supply and to a load; a first comparator with a first node coupled to the load, and a second node coupled to a first reference; a second comparator with a first node coupled to the load, and a second node coupled to a second reference, the second reference being different from the first reference; and a logic unit to receive output of the first comparator and output of the second comparator, the logic unit to turn on or off transistors of the plurality of transistors according to outputs of the first and second comparators.Type: GrantFiled: June 26, 2020Date of Patent: March 5, 2024Assignee: Intel CorporationInventors: Yi-Chun Shih, Kaushik Mazumdar, Stephen T. Kim, Rinkle Jain, James W. Tschanz, Muhammad M. Khellah
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Publication number: 20230198528Abstract: A apparatus includes a reference signal generator, a droop detection circuit, a digital frequency-locked loop (DFLL), and a DFLL control circuit. The reference signal generator that receives a digital value and produces a pulse-density modulated signal based on the digital value. The droop detection circuit converts the pulse-density modulated signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop of the monitored supply voltage below a designated value relative to the analog signal, produces a droop detection signal. The DFLL provides a clock signal for synchronizing circuitry within a domain of the monitored supply voltage. The DFLL control circuit, responsive to receiving the droop detection signal, causes the DFLL to slow the clock signal.Type: ApplicationFiled: December 21, 2021Publication date: June 22, 2023Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Kaushik Mazumdar, Joyce Cheuk Wai Wong, Naeem Ibrahim Ally, Stephen Victor Kosonocky
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Publication number: 20230195191Abstract: A power supply monitor includes a droop detection circuit which receives a digital signal and converts the digital signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop below a designated value relative to the analog signal, produces a droop detection signal. The droop detection circuit includes a first comparator circuit with a series of inverters including at least a first complimentary-metal-oxide-semiconductor (CMOS) inverter with an input for receiving the analog signal and a second CMOS inverter, which are both supplied with a monitored supply voltage. The inverters operate in a crowbar mode when the monitored voltage supply is near a designated level, and each include four pull-up transistors connected in two parallel legs of two transistors, and four pull-down transistors connected in two parallel legs of two transistors.Type: ApplicationFiled: December 22, 2021Publication date: June 22, 2023Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Kaushik Mazumdar, Miguel Rodriguez, Mikhail Rodionov, Stephen Victor Kosonocky
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Publication number: 20230144770Abstract: A method for controlling a data processing system includes detecting a droop in a power supply voltage of a functional circuit of the data processing system greater than a programmable droop threshold. An operation of the data processing system is throttled according to a programmable step size, a programmable assertion time, and a programmable de-assertion time in response to detecting the droop.Type: ApplicationFiled: November 8, 2021Publication date: May 11, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Eric J. Chapman, Stephen Victor Kosonocky, Kaushik Mazumdar, Vydhyanathan Kalyanasundharam, Samuel Naffziger, Eric M. Scott
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Publication number: 20230145626Abstract: A power supply monitor includes a delta-sigma modulator including an input receiving a binary number and an output providing a pulse-density modulated signal, the delta-sigma modulator operable to scale the pulse-density modulated signal based on the binary number. A fast droop detector circuit includes a level shifter providing the modulated signal referenced to a clean supply voltage. A lowpass filter is coupled between the level shifter and a comparator. The comparator produces a droop detection signal at said output responsive to a monitored supply voltage dropping below a predetermined level relative to the filtered signal.Type: ApplicationFiled: November 8, 2021Publication date: May 11, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Miguel Rodriguez, Stephen Victor Kosonocky, Kaushik Mazumdar
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Patent number: 11630161Abstract: A power supply monitor includes a delta-sigma modulator including an input receiving a binary number and an output providing a pulse-density modulated signal, the delta-sigma modulator operable to scale the pulse-density modulated signal based on the binary number. A fast droop detector circuit includes a level shifter providing the modulated signal referenced to a clean supply voltage. A lowpass filter is coupled between the level shifter and a comparator. The comparator produces a droop detection signal at said output responsive to a monitored supply voltage dropping below a predetermined level relative to the filtered signal.Type: GrantFiled: November 8, 2021Date of Patent: April 18, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Miguel Rodriguez, Stephen Victor Kosonocky, Kaushik Mazumdar
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Publication number: 20200393861Abstract: Described is an apparatus which comprises: a plurality of transistors coupled to an input power supply and to a load; a first comparator with a first node coupled to the load, and a second node coupled to a first reference; a second comparator with a first node coupled to the load, and a second node coupled to a second reference, the second reference being different from the first reference; and a logic unit to receive output of the first comparator and output of the second comparator, the logic unit to turn on or off transistors of the plurality of transistors according to outputs of the first and second comparators.Type: ApplicationFiled: June 26, 2020Publication date: December 17, 2020Applicant: Intel CorporationInventors: Yi-Chun Shih, Kaushik Mazumdar, Stephen T. Kim, Rinkle Jain, James W. Tschanz, Muhammad M. Khellah
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Patent number: 10698432Abstract: Described is an apparatus which comprises: a plurality of transistors coupled to an input power supply and to a load; a first comparator with a first node coupled to the load, and a second node coupled to a first reference; a second comparator with a first node coupled to the load, and a second node coupled to a second reference, the second reference being different from the first reference; and a logic unit to receive output of the first comparator and output of the second comparator, the logic unit to turn on or off transistors of the plurality of transistors according to outputs of the first and second comparators.Type: GrantFiled: March 13, 2013Date of Patent: June 30, 2020Assignee: Intel CorporationInventors: Yi-Chun Shih, Kaushik Mazumdar, Stephen T. Kim, Rinkle Jain, James W. Tschanz, Muhammad M. Khellah
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Publication number: 20140277812Abstract: Described is an apparatus which comprises: a plurality of transistors coupled to an input power supply and to a load; a first comparator with a first node coupled to the load, and a second node coupled to a first reference; a second comparator with a first node coupled to the load, and a second node coupled to a second reference, the second reference being different from the first reference; and a logic unit to receive output of the first comparator and output of the second comparator, the logic unit to turn on or off transistors of the plurality of transistors according to outputs of the first and second comparators.Type: ApplicationFiled: March 13, 2013Publication date: September 18, 2014Inventors: Yi-Chun Shih, Kaushik Mazumdar, Stephen T. Kim, Rinkle Jain, James W. Tschanz, Muhammad M. Khellah