Patents by Inventor Kaustuv Manji
Kaustuv Manji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11720735Abstract: Using a flat shell for an accelerator card includes reading a flat shell from one or more computer readable storage media using computer hardware, wherein the flat shell is a synthesized, unplaced, and unrouted top-level circuit design specifying platform circuitry. A kernel specifying user circuitry is synthesized using the computer hardware. The kernel is obtained from the one or more computer readable storage media. The synthesized kernel is linked, using the computer hardware, to the flat shell forming a unified circuit design. The unified circuit design is placed and routed, using the computer hardware, to generate a placed and routed circuit design specifying the platform circuitry and the user circuitry for implementation in an integrated circuit.Type: GrantFiled: August 20, 2021Date of Patent: August 8, 2023Assignee: Xilinx, Inc.Inventors: Sebastian Turullols, Kyle Corbett, Sudipto Chakraborty, Siva Santosh Kumar Pyla, Ravinder Sharma, Kaustuv Manji, Jayaram Pvss, Stephen P. Rozum, Ch Vamshi Krishna, Susheel Puthana
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Publication number: 20230055704Abstract: Using a flat shell for an accelerator card includes reading a flat shell from one or more computer readable storage media using computer hardware, wherein the flat shell is a synthesized, unplaced, and unrouted top-level circuit design specifying platform circuitry. A kernel specifying user circuitry is synthesized using the computer hardware. The kernel is obtained from the one or more computer readable storage media. The synthesized kernel is linked, using the computer hardware, to the flat shell forming a unified circuit design. The unified circuit design is placed and routed, using the computer hardware, to generate a placed and routed circuit design specifying the platform circuitry and the user circuitry for implementation in an integrated circuit.Type: ApplicationFiled: August 20, 2021Publication date: February 23, 2023Applicant: Xilinx, Inc.Inventors: Sebastian Turullols, Kyle Corbett, Sudipto Chakraborty, Siva Santosh Kumar Pyla, Ravinder Sharma, Kaustuv Manji, Jayaram PVSS, Stephen P. Rozum, Ch Vamshi Krishna, Susheel Puthana
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Patent number: 11507394Abstract: Changing accelerator card images without rebooting a host system includes receiving, within an integrated circuit (IC) of an accelerator card, an address of a platform image stored in a non-volatile memory of the accelerator card. The address is received over a communication link between the host system and the accelerator card while the communication link is connected. Changing accelerator card images includes detecting, within a register of the IC, that a warm boot enable flag is set and that the communication link with the host system is disconnected. In response to detecting that the warm boot enable flag is set and that the communication link is disconnected, loading of the platform image from the address of the non-volatile memory into the integrated circuit is initiated.Type: GrantFiled: August 20, 2021Date of Patent: November 22, 2022Assignee: Xilinx, Inc.Inventors: Siva Santosh Kumar Pyla, Ravinder Sharma, Gokul Kavungal Nechikott, Saifuddin Kaijar, Brian S. Martin, Suraj Patel, Rishabh Gupta, Ch Vamshi Krishna, Kaustuv Manji
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Patent number: 11386034Abstract: A hardware acceleration device can include a switch communicatively linked to a host central processing unit (CPU), an adapter coupled to the switch via a control bus, wherein the control bus is configured to convey addresses of descriptors from the host central CPU to the adapter, and a random-access memory (RAM) coupled to the switch through a data bus. The RAM is configured to store descriptors received from the host CPU via the data bus. The hardware acceleration device can include a compute unit coupled to the adapter and configured to perform operations specified by the descriptors. The adapter may be configured to retrieve the descriptors from the RAM via the data bus, provide arguments from the descriptors to the compute unit, and provide control signals to the compute unit to initiate the operations using the arguments.Type: GrantFiled: October 30, 2020Date of Patent: July 12, 2022Assignee: Xilinx, Inc.Inventors: Sonal Santan, Ravi N. Kurlagunda, Min Ma, Himanshu Choudhary, Manjunath Chepuri, Cheng Zhen, Pranjal Joshi, Sebastian Turullols, Amit Kumar, Kaustuv Manji, Ravinder Sharma, Ch Vamshi Krishna
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Publication number: 20220138140Abstract: A hardware acceleration device can include a switch communicatively linked to a host central processing unit (CPU), an adapter coupled to the switch via a control bus, wherein the control bus is configured to convey addresses of descriptors from the host central CPU to the adapter, and a random-access memory (RAM) coupled to the switch through a data bus. The RAM is configured to store descriptors received from the host CPU via the data bus. The hardware acceleration device can include a compute unit coupled to the adapter and configured to perform operations specified by the descriptors. The adapter may be configured to retrieve the descriptors from the RAM via the data bus, provide arguments from the descriptors to the compute unit, and provide control signals to the compute unit to initiate the operations using the arguments.Type: ApplicationFiled: October 30, 2020Publication date: May 5, 2022Applicant: Xilinx, Inc.Inventors: Sonal Santan, Ravi N. Kurlagunda, Min Ma, Himanshu Choudhary, Manjunath Chepuri, Cheng Zhen, Pranjal Joshi, Sebastian Turullols, Amit Kumar, Kaustuv Manji, Ravinder Sharma, Ch Vamshi Krishna
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Patent number: 11029964Abstract: Approaches for configuring a system-on-chip (SOC) include generating component images for components of the SOC. A first component image is for a platform management controller, a second component image is for programmable logic, and a third component image is for a processor subsystem. The plurality of component images are assembled into a programmable device image, and the programmable device image is input to the platform management controller. The platform management controller is booted from the first component image, the programmable logic is configured with the second component image by the platform management controller in executing the first component image, and the processor subsystem is configured with the third component image by the platform management controller in executing the first component image.Type: GrantFiled: February 21, 2019Date of Patent: June 8, 2021Assignee: XLNX, INC.Inventors: Siddharth Rele, Shreegopal S. Agrawal, Kaustuv Manji, Aditya Chaubal