Patents by Inventor Kaveh Moazzami

Kaveh Moazzami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220069774
    Abstract: Techniques are described for using valley detection for supply voltage modulation in power amplifier circuits. Embodiments operate in context of a power amplifier circuit configured to be driven by a supply voltage generated by a supply modulator and to receive an amplitude-modulated (AM) signal at its input. The output of the power amplifier circuit can be fed to a valley detector that can detect a valley level corresponding to the bottom of the envelope of the AM signal. The detected valley level can be fed back to the supply modulator and compared to a constant reference. In response to the comparison, the supply modulator can vary the supply voltage to the power amplifier circuit in a manner that effectively tracking the envelope of the power amplifier circuit's output signal, thereby effectively seeking a flat valley for the output signal's envelope.
    Type: Application
    Filed: November 9, 2021
    Publication date: March 3, 2022
    Inventors: Ahmed Emira, Siavash Yazdi, Kaveh Moazzami
  • Patent number: 11190141
    Abstract: Techniques are described for using valley detection for supply voltage modulation in power amplifier circuits. Embodiments operate in context of a power amplifier circuit configured to be driven by a supply voltage generated by a supply modulator and to receive an amplitude-modulated (AM) signal at its input. The output of the power amplifier circuit can be fed to a valley detector that can detect a valley level corresponding to the bottom of the envelope of the AM signal. The detected valley level can be fed back to the supply modulator and compared to a constant reference. In response to the comparison, the supply modulator can vary the supply voltage to the power amplifier circuit in a manner that effectively tracking the envelope of the power amplifier circuit's output signal, thereby effectively seeking a flat valley for the output signal's envelope.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: November 30, 2021
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Ahmed Emira, Siavash Yazdi, Kaveh Moazzami
  • Publication number: 20200336112
    Abstract: Techniques are described for using valley detection for supply voltage modulation in power amplifier circuits. Embodiments operate in context of a power amplifier circuit configured to be driven by a supply voltage generated by a supply modulator and to receive an amplitude-modulated (AM) signal at its input. The output of the power amplifier circuit can be fed to a valley detector that can detect a valley level corresponding to the bottom of the envelope of the AM signal. The detected valley level can be fed back to the supply modulator and compared to a constant reference. In response to the comparison, the supply modulator can vary the supply voltage to the power amplifier circuit in a manner that effectively tracking the envelope of the power amplifier circuit's output signal, thereby effectively seeking a flat valley for the output signal's envelope.
    Type: Application
    Filed: June 30, 2020
    Publication date: October 22, 2020
    Inventors: Ahmed Emira, Siavash Yazdi, Kaveh Moazzami
  • Patent number: 10763790
    Abstract: Techniques are described for using valley detection for supply voltage modulation in power amplifier circuits. Embodiments operate in context of a power amplifier circuit configured to be driven by a supply voltage generated by a supply modulator and to receive an amplitude-modulated (AM) signal at its input. The output of the power amplifier circuit can be fed to a valley detector that can detect a valley level corresponding to the bottom of the envelope of the AM signal. The detected valley level can be fed back to the supply modulator and compared to a constant reference. In response to the comparison, the supply modulator can vary the supply voltage to the power amplifier circuit in a manner that effectively tracking the envelope of the power amplifier circuit's output signal, thereby effectively seeking a flat valley for the output signal's envelope.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: September 1, 2020
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Ahmed Emira, Siavash Yazdi, Kaveh Moazzami
  • Patent number: 10693462
    Abstract: Techniques are described for ground-intermediating buffering that can effectively use the reference grounds of the circuit domains on either side of a buffer stage to generate one or more intermediated grounds for one or more signal buffers. For example, one of the reference grounds has a first amount of ground noise, the other of the reference grounds has a second amount of ground noise that is greater than or less than the first amount, and the intermediated grounds are generated to have respective amounts of ground noise that are between the first and second amounts. The ground intermediating buffer can perform signal buffering with respect to the intermediated ground(s), thereby reducing ground noise coupling across the circuit domains through both the signal and ground paths of the buffer stage.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: June 23, 2020
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Kaveh Moazzami, Faisal Hussein, Ahmed Emira
  • Publication number: 20200136620
    Abstract: Techniques are described for ground-intermediating buffering that can effectively use the reference grounds of the circuit domains on either side of a buffer stage to generate one or more intermediated grounds for one or more signal buffers. For example, one of the reference grounds has a first amount of ground noise, the other of the reference grounds has a second amount of ground noise that is greater than or less than the first amount, and the intermediated grounds are generated to have respective amounts of ground noise that are between the first and second amounts. The ground intermediating buffer can perform signal buffering with respect to the intermediated ground(s), thereby reducing ground noise coupling across the circuit domains through both the signal and ground paths of the buffer stage.
    Type: Application
    Filed: September 18, 2019
    Publication date: April 30, 2020
    Inventors: Kaveh Moazzami, Faisal Hussein, Ahmed Emira
  • Publication number: 20190379333
    Abstract: Techniques are described for using valley detection for supply voltage modulation in power amplifier circuits. Embodiments operate in context of a power amplifier circuit configured to be driven by a supply voltage generated by a supply modulator and to receive an amplitude-modulated (AM) signal at its input. The output of the power amplifier circuit can be fed to a valley detector that can detect a valley level corresponding to the bottom of the envelope of the AM signal. The detected valley level can be fed back to the supply modulator and compared to a constant reference. In response to the comparison, the supply modulator can vary the supply voltage to the power amplifier circuit in a manner that effectively tracking the envelope of the power amplifier circuit's output signal, thereby effectively seeking a flat valley for the output signal's envelope.
    Type: Application
    Filed: June 6, 2018
    Publication date: December 12, 2019
    Inventors: Ahmed Emira, Siavash Yazdi, Kaveh Moazzami
  • Patent number: 10461749
    Abstract: Techniques are described for ground-intermediating buffering that can effectively use the reference grounds of the circuit domains on either side of a buffer stage to generate one or more intermediated grounds for one or more signal buffers. For example, one of the reference grounds has a first amount of ground noise, the other of the reference grounds has a second amount of ground noise that is greater than or less than the first amount, and the intermediated grounds are generated to have respective amounts of ground noise that are between the first and second amounts. The ground intermediating buffer can perform signal buffering with respect to the intermediated ground(s), thereby reducing ground noise coupling across the circuit domains through both the signal and ground paths of the buffer stage.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: October 29, 2019
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Kaveh Moazzami, Faisal Hussein, Ahmed Emira
  • Patent number: 10312928
    Abstract: Aspects of a method and apparatus for converting an analog input value to a digital output code are provided. One embodiment of the apparatus includes a digital-to-analog converter, a comparator, and control logic circuitry. The digital-to-analog converter is configured to generate an analog reference value based on a received digital reference value. The comparator is configured to compare an analog input value to the analog reference value after expiration of an allotted settling time for the digital-to-analog converter and generate a comparison result indicative a relationship between the analog input value and the analog reference value. The control logic circuitry is configured to select the allotted settling time for the digital-to-analog converter based on a bit position of a digital output code to be determined, and update the bit position of the digital output code based on the comparison result.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: June 4, 2019
    Assignee: MAXLINEAR, INC.
    Inventors: Kaveh Moazzami, Pawan Tiwari, Gaurav Chandra
  • Publication number: 20180269891
    Abstract: Aspects of a method and apparatus for converting an analog input value to a digital output code are provided. One embodiment of the apparatus includes a digital-to-analog converter, a comparator, and control logic circuitry. The digital-to-analog converter is configured to generate an analog reference value based on a received digital reference value. The comparator is configured to compare an analog input value to the analog reference value after expiration of an allotted settling time for the digital-to-analog converter and generate a comparison result indicative a relationship between the analog input value and the analog reference value. The control logic circuitry is configured to select the allotted settling time for the digital-to-analog converter based on a bit position of a digital output code to be determined, and update the bit position of the digital output code based on the comparison result.
    Type: Application
    Filed: May 18, 2018
    Publication date: September 20, 2018
    Inventors: Kaveh Moazzami, Pawan Tiwari, Gaurav Chandra
  • Patent number: 10003350
    Abstract: Aspects of a method and apparatus for converting an analog input value to a digital output code are provided. One embodiment of the apparatus includes a digital-to-analog converter, a comparator, and control logic circuitry. The digital-to-analog converter is configured to generate an analog reference value based on a received digital reference value. The comparator is configured to compare an analog input value to the analog reference value after expiration of an allotted settling time for the digital-to-analog converter and generate a comparison result indicative a relationship between the analog input value and the analog reference value. The control logic circuitry is configured to select the allotted settling time for the digital-to-analog converter based on a bit position of a digital output code to be determined, and update the bit position of the digital output code based on the comparison result.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: June 19, 2018
    Assignee: MAXLINEAR, INC.
    Inventors: Kaveh Moazzami, Pawan Tiwari, Gaurav Chandra
  • Publication number: 20170279459
    Abstract: Aspects of a method and apparatus for converting an analog input value to a digital output code are provided. One embodiment of the apparatus includes a digital-to-analog converter, a comparator, and control logic circuitry. The digital-to-analog converter is configured to generate an analog reference value based on a received digital reference value. The comparator is configured to compare an analog input value to the analog reference value after expiration of an allotted settling time for the digital-to-analog converter and generate a comparison result indicative a relationship between the analog input value and the analog reference value. The control logic circuitry is configured to select the allotted settling time for the digital-to-analog converter based on a bit position of a digital output code to be determined, and update the bit position of the digital output code based on the comparison result.
    Type: Application
    Filed: June 8, 2017
    Publication date: September 28, 2017
    Inventors: Kaveh Moazzami, Pawan Tiwari, Gaurav Chandra
  • Patent number: 9698811
    Abstract: Aspects of a method and apparatus for converting an analog input value to a digital output code are provided. One embodiment of the apparatus includes a digital-to-analog converter, a comparator, and control logic circuitry. The digital-to-analog converter is configured to generate an analog reference value based on a received digital reference value. The comparator is configured to compare an analog input value to the analog reference value after expiration of an allotted settling time for the digital-to-analog converter and generate a comparison result indicative a relationship between the analog input value and the analog reference value. The control logic circuitry is configured to select the allotted settling time for the digital-to-analog converter based on a bit position of a digital output code to be determined, and update the bit position of the digital output code based on the comparison result.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: July 4, 2017
    Assignee: MAXLINEAR, INC.
    Inventors: Kaveh Moazzami, Pawan Tiwari, Gaurav Chandra
  • Patent number: 9503667
    Abstract: A method to read out pixels includes reading a first pixel by resetting a first photodetector, integrating the first photodetector after resetting the first photodetector, resetting a first floating diffusion node coupled to the first photodetector and a second floating diffusion node coupled to a second photodetector, transferring charge from the first photodetector to the first floating diffusion node, comparing a first signal at the first floating diffusion node and a second signal at the second floating diffusion node and generating a first signal to latch a first counter value when the first signal is less than the second signal, incrementing the first signal and decrementing the second signal, and comparing the first signal and the second signal and generating a second signal to latch a second counter value when the first signal is greater than the second signal, wherein the difference between the second counter value and the first counter value indicates a first pixel level.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: November 22, 2016
    Assignee: HIMAX IMAGING, INC.
    Inventors: Ping Hung Yin, Amit Mittra, Kaveh Moazzami, Kwangoh Kim, Satya Narayan Mishra
  • Publication number: 20160329908
    Abstract: Aspects of a method and apparatus for converting an analog input value to a digital output code are provided. One embodiment of the apparatus includes a digital-to-analog converter, a comparator, and control logic circuitry. The digital-to-analog converter is configured to generate an analog reference value based on a received digital reference value. The comparator is configured to compare an analog input value to the analog reference value after expiration of an allotted settling time for the digital-to-analog converter and generate a comparison result indicative a relationship between the analog input value and the analog reference value. The control logic circuitry is configured to select the allotted settling time for the digital-to-analog converter based on a bit position of a digital output code to be determined, and update the bit position of the digital output code based on the comparison result.
    Type: Application
    Filed: May 9, 2016
    Publication date: November 10, 2016
    Inventors: Kaveh Moazzami, Pawan Tiwari, Gaurav Chandra
  • Patent number: 9362941
    Abstract: Aspects of a method and apparatus for converting an analog input value to a digital output code are provided. One embodiment of the apparatus includes a digital-to-analog converter, a comparator, and control logic circuitry. The digital-to-analog converter is configured to generate an analog reference value based on a received digital reference value. The comparator is configured to compare an analog input value to the analog reference value after expiration of an allotted settling time for the digital-to-analog converter and generate a comparison result indicative a relationship between the analog input value and the analog reference value. The control logic circuitry is configured to select the allotted settling time for the digital-to-analog converter based on a bit position of a digital output code to be determined, and update the bit position of the digital output code based on the comparison result.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: June 7, 2016
    Assignee: MAXLINEAR, INC.
    Inventors: Kaveh Moazzami, Pawan Tiwari, Gaurav Chandra
  • Publication number: 20150280731
    Abstract: Aspects of a method and apparatus for converting an analog input value to a digital output code are provided. One embodiment of the apparatus includes a digital-to-analog converter, a comparator, and control logic circuitry. The digital-to-analog converter is configured to generate an analog reference value based on a received digital reference value. The comparator is configured to compare an analog input value to the analog reference value after expiration of an allotted settling time for the digital-to-analog converter and generate a comparison result indicative a relationship between the analog input value and the analog reference value. The control logic circuitry is configured to select the allotted settling time for the digital-to-analog converter based on a bit position of a digital output code to be determined, and update the bit position of the digital output code based on the comparison result.
    Type: Application
    Filed: June 12, 2015
    Publication date: October 1, 2015
    Inventors: Kaveh Moazzami, Pawan Tiwari, Gaurav Chandra
  • Patent number: 9143708
    Abstract: A pixel array comprises at least one long exposure pixel, short exposure pixel, and a control circuit. The long exposure pixel comprises a first photodiode to generate charges, a first image signal generating module for generating a first image sensing signal; and a first transfer switch device for passing the charges to the first image signal generating module via a first transfer control signal. The control circuit sets the first transfer control signal to be a first predetermined control voltage when the long exposure pixel is in an long exposure phase, and then sets the first transfer control signal to be a second predetermined control voltage when the short exposure pixel is in a short exposure phase.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: September 22, 2015
    Assignee: Himax Imaging, Inc.
    Inventors: Ping-Hung Yin, Amit Mittra, Kaveh Moazzami, Satya Narayan Mishra
  • Patent number: 9083376
    Abstract: Aspects of a method and apparatus for converting an analog input value to a digital output code are provided. One embodiment of the apparatus includes a digital-to-analog converter, a comparator, and control logic circuitry. The digital-to-analog converter is configured to generate an analog reference value based on a received digital reference value. The comparator is configured to compare an analog input value to the analog reference value after expiration of an allotted settling time for the digital-to-analog converter and generate a comparison result indicative a relationship between the analog input value and the analog reference value. The control logic circuitry is configured to select the allotted settling time for the digital-to-analog converter based on a bit position of a digital output code to be determined, and update the bit position of the digital output code based on the comparison result.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: July 14, 2015
    Assignee: MAXLINEAR, INC.
    Inventors: Kaveh Moazzami, Pawan Tiwari, Gaurav Chandra
  • Publication number: 20150170329
    Abstract: A signal processing apparatus includes a correlated double sampling unit and a processing unit. The correlated double sampling unit is arranged for receiving a reset signal and a data signal, obtaining a reset level and a first data level corresponding to the reset signal and the data signal, respectively, and outputting an output signal according to a level difference between the reset level and the first data level. The processing unit is coupled to the correlated double sampling unit, and is arranged for receiving a second data level of the data signal and a predetermined level, and comparing the second data level with the predetermined level to generate a detection result indicative of quality of the level difference.
    Type: Application
    Filed: February 24, 2015
    Publication date: June 18, 2015
    Inventors: Ping-Hung Yin, Kaveh Moazzami, Satya Narayan Mishra, Amit Mittra