Patents by Inventor Kayoko Nemoto

Kayoko Nemoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6657459
    Abstract: A semiconductor integrated circuit device, responsive to an input signal having a low amplitude and short transition time, operates with low power consumption and prevents the flow of breakthrough current. In an example circuit thereof, the input signal is transmitted through an NMOS pass transistor to the gate of a first NMOS transistor and is applied, through a second NMOS transistor, to the gate of a first PMOS transistor, the first PMOS transistor performing complementary operation with the first NMOS transistor through the second NMOS transistor; the gate of the first PMOS transistor is connected to the power supply potential through the second PMOS transistor; the gate of the second NMOS transistor is connected to the power supply potential; and the gate of the second PMOS transistor is controlled by the signal at a common drain connection of the first NMOS and first PMOS transistors.
    Type: Grant
    Filed: May 14, 2002
    Date of Patent: December 2, 2003
    Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.
    Inventors: Yoji Nishio, Kosaku Hirose, Hideo Hara, Katsunori Koike, Kayoko Nemoto, Tatsumi Yamauchi, Fumio Murabayashi, Hiromichi Yamada
  • Patent number: 6462580
    Abstract: The object of the present invention to provide a semiconductor integrated circuit device wherein the input signal is made to have a low amplitude to shorten transition time of the input signal, said integrated circuit device operating at a low power consumption, without flowing of breakthrough current, despite entry of the input signal featuring low-amplitude operations, and said integrated circuit device comprising a gate circuit, memory and processor.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: October 8, 2002
    Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.
    Inventors: Yoji Nishio, Kosaku Hirose, Hideo Hara, Katsunori Koike, Kayoko Nemoto, Tatsumi Yamauchi, Fumio Murabayashi, Hiromichi Yamada
  • Publication number: 20020130683
    Abstract: A semiconductor integrated circuit device, responsive to an input signal having a low amplitude and short transition time, operates with low power consumption and prevents the flow of breakthrough current. In an example circuit thereof, the input signal is transmitted through an NMOS pass transistor to the gate of a first NMOS transistor and is applied, through a second NMOS transistor, to the gate of a first PMOS transistor, the first PMOS transistor performing complementary operation with the first NMOS transistor through the second NMOS transistor; the gate of the first PMOS transistor is connected to the power supply potential through the second PMOS transistor; the gate of the second NMOS transistor is connected to the power supply potential; and the gate of the second PMOS transistor is controlled by the signal at a common drain connection of the first NMOS and first PMOS transistors.
    Type: Application
    Filed: May 14, 2002
    Publication date: September 19, 2002
    Inventors: Yoji Nishio, Kosaku Hirose, Hideo Hara, Katsunori Koike, Kayoko Nemoto, Tatsumi Yamauchi, Fumio Murabayashi, Hiromichi Yamada
  • Publication number: 20010000653
    Abstract: The object of the present invention is to provide a semiconductor integrated circuit device wherein the input signal is made to have a low amplitude to shorten transition time of the input signal, said integrated circuit device operating at a low power consumption, without flowing of breakthrough current, despite entry of the input signal featuring low-amplitude operations, and said integrated circuit device comprising a gate circuit, memory and processor.
    Type: Application
    Filed: December 28, 2000
    Publication date: May 3, 2001
    Inventors: Yoji Nishio, Kosaku Hirose, Hideo Hara, Katsunori Koike, Kayoko Nemoto, Tatsumi Yamauchi, Fumio Murabayashi, Hiromichi Yamada
  • Patent number: 6172532
    Abstract: The object of the present invention is to provide a semiconductor integrated circuit device wherein the input signal is made to have a low amplitude to shorten transition time of the input signal, said integrated circuit device operating at a low power consumption, without flowing of breakthrough current, despite entry of the input signal featuring low-amplitude operations, and said integrated circuit device comprising a gate circuit, memory and processor.
    Type: Grant
    Filed: September 8, 1997
    Date of Patent: January 9, 2001
    Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.
    Inventors: Yoji Nishio, Kosaku Hirose, Hideo Hara, Katsunori Koike, Kayoko Nemoto, Tatsumi Yamauchi, Fumio Murabayashi, Hiromichi Yamada
  • Patent number: 5677641
    Abstract: The object of the present invention is to provide a semiconductor integrated circuit device wherein the input signal is made to have a low amplitude to shorten transition time of the input signal, said integrated circuit device operating at a low power consumption, without flowing of breakthrough current, despite entry of the input signal featuring low-amplitude operations, and said integrated circuit device comprising a gate circuit, memory and processor.
    Type: Grant
    Filed: April 18, 1995
    Date of Patent: October 14, 1997
    Assignees: Hitachi Ltd., Hitachi Engineering Co., Ltd.
    Inventors: Yoji Nishio, Kosaku Hirose, Hideo Hara, Katsunori Koike, Kayoko Nemoto, Tatsumi Yamauchi, Fumio Murabayashi, Hiromichi Yamada
  • Patent number: 4642621
    Abstract: Two different CT images are stored respectively in a primary image memory and a secondary image memory. For image display, the secondary image is inset in a desired rectangular region in the main image memory so that the two images can simultaneously be displayed. The data for the two images to be displayed can be independently subjected to various types of processing in real time, such as window or level processing, blinking for flashing displayed image data pixels in a particular CT value zone, and reverse video operations.
    Type: Grant
    Filed: March 27, 1984
    Date of Patent: February 10, 1987
    Assignee: Yokogawa Medical Systems, Limited
    Inventors: Kayoko Nemoto, Takeshi Ohya