Patents by Inventor Kazuaki DOI

Kazuaki DOI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10678161
    Abstract: An electrophotographic member has an electro-conductive substrate, an elastic layer on the substrate and a coating layer on the elastic layer. The elastic layer has an elastic modulus of 0.5 MPa to 3.0 MPa and the coating layer has an elastic modulus of 5.0 MPa to 100.0 MPa as measured in an environment of a temperature of 30° C. and a relative humidity of 80%.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: June 9, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Seiji Tsuru, Noriyuki Doi, Ryo Sugiyama, Kazuaki Nagaoka, Minoru Nakamura
  • Patent number: 10640885
    Abstract: A method for a SiC single crystal that allow prolonged growth to be achieved are provided. A method for producing a SiC single crystal in which a seed crystal substrate held on a seed crystal holding shaft is contacted with a Si—C solution having a temperature gradient such that a temperature of the Si—C solution decreases from an interior of the Si—C solution toward a liquid level of the Si—C solution, in a graphite crucible, to grow a SiC single crystal, wherein the method comprises the steps of: electromagnetic stirring of the Si—C solution with an induction coil to produce a flow, and heating of a lower part of the graphite crucible with a resistance heater.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: May 5, 2020
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Masayoshi Doi, Hironori Daikoku, Motohisa Kado, Tomohiro Sato, Kazuaki Seki, Kazuhiko Kusunoki, Yutaka Kishida
  • Publication number: 20200092089
    Abstract: According to an embodiment, an information processor includes a memory and one or more hardware processors coupled to the memory. The one or more hardware processors are configured to function as a calculating unit, a determining unit, and a generating unit. The calculating unit is configured to calculate a key length. The determining unit is configured to determine a block size corresponding to a unit of processing in key generation and an outputtable size indicating the size of a key outputtable by the key generation. The generating unit is configured to generate a key having the key length by a hash operation using a matrix having a size determined by the block size and the outputtable size.
    Type: Application
    Filed: February 28, 2019
    Publication date: March 19, 2020
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ririka TAKAHASHI, Yoshimichi TANIZAWA, Kazuaki DOI, Mamiko KUJIRAOKA, Akira MURAKAMI
  • Publication number: 20200041928
    Abstract: To provide an electrophotographic member causing less change in toner conveyance even used in a high-temperature and high-humidity environment. The electrophotographic member has an electro-conductive substrate, an elastic layer on the substrate and a coating layer on the elastic layer. The elastic layer has a first protrusion on a surface thereof on a side opposite to a side facing the substrate. The electrophotographic member has, on an outer surface thereof, a second protrusion derived from the first protrusion. The outer surface of the electrophotographic member has one or more of electrical insulating first region(s) and an electro-conductive second region. The elastic layer has an elastic modulus of 0.5 MPa or more to 3.0 MPa or less and the coating layer has an elastic modulus of 5.0 MPa or more to 100.0 MPa or less as measured in an environment of a temperature of 30° C. and a relative humidity of 80%.
    Type: Application
    Filed: July 30, 2019
    Publication date: February 6, 2020
    Inventors: Seiji Tsuru, Noriyuki Doi, Ryo Sugiyama, Kazuaki Nagaoka, Minoru Nakamura
  • Patent number: 10348492
    Abstract: According to an embodiment, a quantum key distribution device includes first and second operation units. The first operation unit is configured to perform a first operation as a key distillation operation. The first operation unit includes a hardware circuit for performing a part of the first operation. The key distillation operation includes a sifting operation for a photon bit string generated through quantum key distribution with another quantum key distribution device via a quantum communication channel. The second operation unit is configured to perform a second operation as a key distillation operation other than the first operation. The second operation unit includes a circuit for a part of the second operation. The first operation unit stores intermediate data generated by the first operation. The second operation unit generates, by the second operation, a cryptographic key being the same as for the another quantum key distribution device from the intermediate data.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: July 9, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshimichi Tanizawa, Hideaki Sato, Kazuaki Doi, Ririka Takahashi, Akira Murakami
  • Patent number: 10256838
    Abstract: According to an embodiment, a decoding apparatus for a low-density parity-check (LDPC) code includes a first calculator, a second calculator, and a selector. The first calculator is configured to perform row processing based on a first decoding algorithm. The second calculator is configured to perform row processing based on a second decoding algorithm having a lower error correction capacity than that of the first decoding algorithm. The selector is configured to select an output value from the row processing performed by the second calculator when an error in an output value from the row processing performed by the first calculator is greater than an error in the output value from the row processing performed by the second calculator.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: April 9, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazuaki Doi
  • Publication number: 20180359086
    Abstract: According to an embodiment, a quantum communication device includes a corrector and a retransmission controller. The corrector is configured to generate corrected key data by performing error correction on received key data received from a transmitting device through a quantum channel. The retransmission controller is configured to transmit a retransmission request including retransmission target address information to the transmitting device through a control channel when a retransmission request condition is satisfied, and receive retransmission key data corresponding to the retransmission target address information from the transmitting device through the control channel. After receiving the retransmission key data, the corrector replaces corrected key data corresponding to the retransmission target address information with the retransmission key data.
    Type: Application
    Filed: February 16, 2018
    Publication date: December 13, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Alex Dixon, Kazuaki Doi
  • Publication number: 20180262328
    Abstract: According to an embodiment, a quantum communication device is adapted to correct first sift key data acquired by performing sift processing with respect to a quantum bit string received from a transmission device via a quantum communication path. The quantum communication device includes a determination unit and a correction unit. The determination unit determines setting information of error correction on the first sift key data from an estimated error rate of the first sift key data and a margin of the estimated error rate. The correction unit generates corrected key data by performing the error correction with the setting information.
    Type: Application
    Filed: August 24, 2017
    Publication date: September 13, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazuaki Doi, Yoshimichi Tanizawa
  • Patent number: 9652620
    Abstract: According to an embodiment, a quantum communication device includes a sift processor, an estimator, a determination unit, and a corrector. The sift processor is configured to acquire sift processing data by referring to a cryptographic key bit string in a predetermined bit string with a reference basis randomly selected from a plurality of bases via a quantum communication channel. The estimator is configured to acquire an estimated error rate of the sift processing data. The determination unit is configured to determine order of the sift processing data in which an error is to be corrected based on the estimated error rate and difference data between a processing speed of error correcting processing and a processing speed of privacy amplification processing. The corrector is configured to acquire one piece of the sift processing data in the order determined by the determination unit, and generate error correcting processing data.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: May 16, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuaki Doi, Yoshimichi Tanizawa
  • Patent number: 9569731
    Abstract: According to an embodiment, a quantum communication device includes a receiver, a sift processor, an estimator, first and second storages, a determination unit, an error corrector, a measurement unit, and a privacy amplifier. The sift processor acquires sift processing data by referring to a cryptographic key bit string in a predetermined bit string with a reference basis randomly selected from a plurality of bases. The estimator acquires an estimated error rate by estimating an error rate of the sift processing data from an error rate of part of the sift processing data. When a sift processing data volume stored in the first storage is not smaller than a first threshold, the determination unit determines order of the sift processing data to be corrected based on an estimated error rate, an error rate range that a check matrix can correct, and estimated correction time, and the check matrix used for correction.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: February 14, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuaki Doi, Yoshimichi Tanizawa
  • Publication number: 20160329909
    Abstract: According to an embodiment, a decoding apparatus for a low-density parity-check (LDPC) code includes a first calculator, a second calculator, and a selector. The first calculator is configured to perform row processing based on a first decoding algorithm. The second calculator is configured to perform row processing based on a second decoding algorithm having a lower error correction capacity than that of the first decoding algorithm. The selector is configured to select an output value from the row processing performed by the second calculator when an error in an output value from the row processing performed by the first calculator is greater than an error in the output value from the row processing performed by the second calculator.
    Type: Application
    Filed: February 16, 2016
    Publication date: November 10, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kazuaki DOI
  • Publication number: 20160142203
    Abstract: According to an embodiment, a quantum key distribution device includes first and second operation units. The first operation unit is configured to perform a first operation as a key distillation operation. The first operation unit includes a hardware circuit for performing a part of the first operation. The key distillation operation includes a sifting operation for a photon bit string generated through quantum key distribution with another quantum key distribution device via a quantum communication channel. The second operation unit is configured to perform a second operation as a key distillation operation other than the first operation. The second operation unit includes a circuit for a part of the second operation. The first operation unit stores intermediate data generated by the first operation. The second operation unit generates, by the second operation, a cryptographic key being the same as for the another quantum key distribution device from the intermediate data.
    Type: Application
    Filed: September 30, 2015
    Publication date: May 19, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yoshimichi TANIZAWA, Hideaki SATO, Kazuaki DOI, Ririka TAKAHASHI, Akira MURAKAMI
  • Patent number: 9240805
    Abstract: According to an embodiment, in a parity check matrix creation method, all N column vectors in the mask matrix are different. A submatrix having M rows×L columns obtained by arbitrarily extracting L continuous columns from the mask matrix includes B1 first correction rows and Bi ith correction rows. The B1 first correction rows have at least one “1” in total in each of A1 first correction columns. Each of the Bi ith correction rows has at least one “1” in total in Ai?1 (i?1)th correction columns and has “1” in one of Ai ith correction columns included in a column set excluding the first correction columns to (i?1)th correction columns. The Bi ith correction rows include at least one “1” in total in each of the Ai ith correction columns. A sum from A1 to AI equals L.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: January 19, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuaki Doi, Akihito Ogawa, Hironori Uchikawa
  • Publication number: 20150381210
    Abstract: According to an embodiment, in a parity check matrix creation method, all of N column vectors in the mask matrix are different from each other. The B1 first correction rows have at least one “1” in total in each of A1 first correction columns. Each of the Bi ith correction rows has at least one “1” in total in Ai?1 (i?1)th correction columns. Each of the Bi ith correction rows has “1” in one of Ai ith correction columns included in a column set excluding the first correction column to an (i?1)th correction column. The Bi ith correction rows include at least one “1” in total in each of the Ai ith correction columns. A sum from B1 to BI?1 equals a sum of S and a sum from A1 to AI?1.
    Type: Application
    Filed: September 8, 2015
    Publication date: December 31, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuaki DOI, Akihito OGAWA
  • Patent number: 9117485
    Abstract: According to an embodiment, a signal processing apparatus includes a first signal processor, a second signal processor and a third signal processor. The first signal processor suppresses an offset component remaining in a reproduction signal read from an optical recording medium to obtain a first signal. The second signal processor suppresses a nonlinear distortion component remaining in the first signal to obtain a second signal. The third signal processor suppresses a correlation noise component remaining in the second signal to obtain a third signal.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: August 25, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akihito Ogawa, Kazuaki Doi
  • Patent number: 9087523
    Abstract: According to one embodiment, in an information recording medium including a plurality of data layers, at least one pre-format area is provided on each of the data layers and is circumferentially divided into a plurality of segments. Management information including data layer identification information for identifying the data layers is recorded in at least one of the segments in each of the data layers, using the marks include BCA marks extending radially uniformly. On adjacent ones of the data layers, the BCA marks associated with the management information are recorded in differently positioned segments which are not opposed to each other.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: July 21, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akihito Ogawa, Kazuo Watabe, Hideaki Okano, Takashi Usui, Hidefumi Takamine, Kazuaki Doi, Masahiro Saito
  • Publication number: 20150195087
    Abstract: According to an embodiment, a quantum communication device includes a receiver, a sift processor, an estimator, first and second storages, a determination unit, an error corrector, a measurement unit, and a privacy amplifier. The sift processor acquires sift processing data by referring to a cryptographic key bit string in a predetermined bit string with a reference basis randomly selected from a plurality of bases. The estimator acquires an estimated error rate by estimating an error rate of the sift processing data from an error rate of part of the sift processing data. When a sift processing data volume stored in the first storage is not smaller than a first threshold, the determination unit determines order of the sift processing data to be corrected based on an estimated error rate, an error rate range that a check matrix can correct, and estimated correction time, and the check matrix used for correction.
    Type: Application
    Filed: January 6, 2015
    Publication date: July 9, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazuaki DOI, Yoshimichi Tanizawa
  • Publication number: 20150193306
    Abstract: According to an embodiment, a quantum communication device includes a sift processor, an estimator, a determination unit, and a corrector. The sift processor is configured to acquire sift processing data by referring to a cryptographic key bit string in a predetermined bit string with a reference basis randomly selected from a plurality of bases via a quantum communication channel. The estimator is configured to acquire an estimated error rate of the sift processing data. The determination unit is configured to determine order of the sift processing data in which an error is to be corrected based on the estimated error rate and difference data between a processing speed of error correcting processing and a processing speed of privacy amplification processing. The corrector is configured to acquire one piece of the sift processing data in the order determined by the determination unit, and generate error correcting processing data.
    Type: Application
    Filed: December 22, 2014
    Publication date: July 9, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazuaki DOI, Yoshimichi TANIZAWA
  • Patent number: 9064506
    Abstract: According to one embodiment, an information recording and reproducing apparatus including, a focus control module, an objective lens control module, a calculation module, and a tracking control module. If, detection the recording marks line, to focus a laser light of a second wavelength to the recording layer through an objective lens and to operation a recording layer tracking control using a tracking error signal taken out from a second reflected light and a laser light of a first wavelength to a track groove through the objective lens and to operation a guide layer tracking control to control the objective lens using a tracking error signal taken out from a first reflected light.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: June 23, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hideaki Okano, Kazuo Watabe, Chikara Tanioka, Akihito Ogawa, Takashi Usui, Kazuaki Doi
  • Publication number: 20150006989
    Abstract: According to an embodiment, in a parity check matrix creation method, all N column vectors in the mask matrix are different. A submatrix having M rows×L columns obtained by arbitrarily extracting L continuous columns from the mask matrix includes B1 first correction rows and Bi ith correction rows. The B1 first correction rows have at least one “1” in total in each of A1 first correction columns. Each of the Bi ith correction rows has at least one “1” in total in Ai-1 (i?1)th correction columns and has “1” in one of Ai ith correction columns included in a column set excluding the first correction columns to (i?1)th correction columns. The Bi ith correction rows include at least one “1” in total in each of the Ai ith correction columns. A sum from A1 to AI equals L.
    Type: Application
    Filed: September 16, 2014
    Publication date: January 1, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuaki DOI, Akihito Ogawa, Hironori Uchikawa