Abstract: According to an embodiment, an interleave circuit includes a reordering circuit and an address calculation circuit. The reordering circuit is configured to, for each cycle, receive in parallel input data containing n (n is an integer of 2 or more) bits, and reorder n-pieces of the input data input in n cycles into n-pieces of output data each containing n bits input in cycles different from each other. The address calculation circuit is configured to calculate write addresses for writing the n-pieces of output data into a first storage device and read addresses for reading out the n-pieces of output data from the first storage device.

Abstract: According to an embodiment, a quantum cryptographic communication system includes a first quantum key distribution (QKD) device, and a first key management device. The first QKD device that shares a quantum encryption key with a second QKD device through QKD. The first key management device includes a reception unit and a first hardware security module (HSM). The reception unit receives the quantum encryption key from the first QKD device. The first HSM includes a storage unit, a generation unit, and a first encryption unit. The storage unit stores a first encryption key therein. The generation unit generates an application key used in an encryption process by a cryptographic application. The first encryption unit that encrypts, with the first encryption key, the application key transmitted to a second key management device connected to the second QKD device.

Abstract: According to an embodiment, an application-key management system includes a plurality of application-key management devices and a comprehensive management device. The application-key management devices each include: a first memory configured to store an application key in one or more separated logical drives for each sharing destination of the application key shared by quantum cryptographic communication; and a first processor coupled to the first memory. The first processor is configured to: receive, from the comprehensive management device, a deletion request of specifying a logical drive storing the application key to be deleted among the logical drives; and delete the application key stored in the logical drive specified by the deletion request.

Abstract: A quantum-cryptographic-communication system according to an embodiment includes a key-integrated-management device, quantum-cryptography devices, and key-management-inspection devices. An inspection-target-value-calculating unit calculates an inspection-target value based on quantum-cryptography-device information related to a quantum-cryptography device. An expected-value-calculating unit calculates an expected value based on at least one of wiring information of a QKD link connected to the inspection-target-quantum-cryptography device; weather information of the site installed with the inspection-target-quantum-cryptography device; and the quantum-cryptography-device information. A permissible-value-calculating unit calculates a permissible value based on at least one of the wiring information, the weather information, and the quantum-cryptography-device information.

Abstract: According to an embodiment, a quantum communication device is adapted to correct first sift key data acquired by performing sift processing with respect to a quantum bit string received from a transmission device via a quantum communication path. The quantum communication device includes a determination unit and a correction unit. The determination unit determines setting information of error correction on the first sift key data from an estimated error rate of the first sift key data and a margin of the estimated error rate. The correction unit generates corrected key data by performing the error correction with the setting information.

Abstract: According to an embodiment, an application-key management system includes a plurality of application-key management devices and a comprehensive management device. The application-key management devices each include: a first memory configured to store an application key in one or more separated logical drives for each sharing destination of the application key shared by quantum cryptographic communication; and a first processor coupled to the first memory. The first processor is configured to: receive, from the comprehensive management device, a deletion request of specifying a logical drive storing the application key to be deleted among the logical drives; and delete the application key stored in the logical drive specified by the deletion request.

Abstract: According to an embodiment, a quantum cryptographic device includes a memory and one or more processors coupled to the memory. The one or more processors are configured to: tabulate information on an application key transmitted and received by using a quantum cryptographic key and output an application-key information tabulation result; calculate a unit price of the application key based on the application-key information tabulation result; and display information that is display information including the unit price of the application key.

Abstract: According to an embodiment, an information processor includes a memory and one or more hardware processors coupled to the memory. The one or more hardware processors are configured to function as a calculating unit, a determining unit, and a generating unit. The calculating unit is configured to calculate a key length. The determining unit is configured to determine a block size corresponding to a unit of processing in key generation and an outputtable size indicating the size of a key outputtable by the key generation. The generating unit is configured to generate a key having the key length by a hash operation using a matrix having a size determined by the block size and the outputtable size.

Abstract: According to an embodiment, an information processor includes a memory and one or more hardware processors coupled to the memory. The one or more hardware processors are configured to function as a calculating unit, a determining unit, and a generating unit. The calculating unit is configured to calculate a key length. The determining unit is configured to determine a block size corresponding to a unit of processing in key generation and an outputtable size indicating the size of a key outputtable by the key generation. The generating unit is configured to generate a key having the key length by a hash operation using a matrix having a size determined by the block size and the outputtable size.

Abstract: According to an embodiment, a quantum key distribution device includes first and second operation units. The first operation unit is configured to perform a first operation as a key distillation operation. The first operation unit includes a hardware circuit for performing a part of the first operation. The key distillation operation includes a sifting operation for a photon bit string generated through quantum key distribution with another quantum key distribution device via a quantum communication channel. The second operation unit is configured to perform a second operation as a key distillation operation other than the first operation. The second operation unit includes a circuit for a part of the second operation. The first operation unit stores intermediate data generated by the first operation. The second operation unit generates, by the second operation, a cryptographic key being the same as for the another quantum key distribution device from the intermediate data.

Abstract: According to an embodiment, a decoding apparatus for a low-density parity-check (LDPC) code includes a first calculator, a second calculator, and a selector. The first calculator is configured to perform row processing based on a first decoding algorithm. The second calculator is configured to perform row processing based on a second decoding algorithm having a lower error correction capacity than that of the first decoding algorithm. The selector is configured to select an output value from the row processing performed by the second calculator when an error in an output value from the row processing performed by the first calculator is greater than an error in the output value from the row processing performed by the second calculator.

Abstract: According to an embodiment, a quantum communication device includes a corrector and a retransmission controller. The corrector is configured to generate corrected key data by performing error correction on received key data received from a transmitting device through a quantum channel. The retransmission controller is configured to transmit a retransmission request including retransmission target address information to the transmitting device through a control channel when a retransmission request condition is satisfied, and receive retransmission key data corresponding to the retransmission target address information from the transmitting device through the control channel. After receiving the retransmission key data, the corrector replaces corrected key data corresponding to the retransmission target address information with the retransmission key data.

Abstract: According to an embodiment, a quantum communication device is adapted to correct first sift key data acquired by performing sift processing with respect to a quantum bit string received from a transmission device via a quantum communication path. The quantum communication device includes a determination unit and a correction unit. The determination unit determines setting information of error correction on the first sift key data from an estimated error rate of the first sift key data and a margin of the estimated error rate. The correction unit generates corrected key data by performing the error correction with the setting information.

Abstract: According to an embodiment, a quantum communication device includes a sift processor, an estimator, a determination unit, and a corrector. The sift processor is configured to acquire sift processing data by referring to a cryptographic key bit string in a predetermined bit string with a reference basis randomly selected from a plurality of bases via a quantum communication channel. The estimator is configured to acquire an estimated error rate of the sift processing data. The determination unit is configured to determine order of the sift processing data in which an error is to be corrected based on the estimated error rate and difference data between a processing speed of error correcting processing and a processing speed of privacy amplification processing. The corrector is configured to acquire one piece of the sift processing data in the order determined by the determination unit, and generate error correcting processing data.

Abstract: According to an embodiment, a quantum communication device includes a receiver, a sift processor, an estimator, first and second storages, a determination unit, an error corrector, a measurement unit, and a privacy amplifier. The sift processor acquires sift processing data by referring to a cryptographic key bit string in a predetermined bit string with a reference basis randomly selected from a plurality of bases. The estimator acquires an estimated error rate by estimating an error rate of the sift processing data from an error rate of part of the sift processing data. When a sift processing data volume stored in the first storage is not smaller than a first threshold, the determination unit determines order of the sift processing data to be corrected based on an estimated error rate, an error rate range that a check matrix can correct, and estimated correction time, and the check matrix used for correction.

Abstract: According to an embodiment, a decoding apparatus for a low-density parity-check (LDPC) code includes a first calculator, a second calculator, and a selector. The first calculator is configured to perform row processing based on a first decoding algorithm. The second calculator is configured to perform row processing based on a second decoding algorithm having a lower error correction capacity than that of the first decoding algorithm. The selector is configured to select an output value from the row processing performed by the second calculator when an error in an output value from the row processing performed by the first calculator is greater than an error in the output value from the row processing performed by the second calculator.

Abstract: According to an embodiment, a quantum key distribution device includes first and second operation units. The first operation unit is configured to perform a first operation as a key distillation operation. The first operation unit includes a hardware circuit for performing a part of the first operation. The key distillation operation includes a sifting operation for a photon bit string generated through quantum key distribution with another quantum key distribution device via a quantum communication channel. The second operation unit is configured to perform a second operation as a key distillation operation other than the first operation. The second operation unit includes a circuit for a part of the second operation. The first operation unit stores intermediate data generated by the first operation. The second operation unit generates, by the second operation, a cryptographic key being the same as for the another quantum key distribution device from the intermediate data.

Abstract: According to an embodiment, in a parity check matrix creation method, all N column vectors in the mask matrix are different. A submatrix having M rows×L columns obtained by arbitrarily extracting L continuous columns from the mask matrix includes B1 first correction rows and Bi ith correction rows. The B1 first correction rows have at least one “1” in total in each of A1 first correction columns. Each of the Bi ith correction rows has at least one “1” in total in Ai?1 (i?1)th correction columns and has “1” in one of Ai ith correction columns included in a column set excluding the first correction columns to (i?1)th correction columns. The Bi ith correction rows include at least one “1” in total in each of the Ai ith correction columns. A sum from A1 to AI equals L.

Abstract: According to an embodiment, in a parity check matrix creation method, all of N column vectors in the mask matrix are different from each other. The B1 first correction rows have at least one “1” in total in each of A1 first correction columns. Each of the Bi ith correction rows has at least one “1” in total in Ai?1 (i?1)th correction columns. Each of the Bi ith correction rows has “1” in one of Ai ith correction columns included in a column set excluding the first correction column to an (i?1)th correction column. The Bi ith correction rows include at least one “1” in total in each of the Ai ith correction columns. A sum from B1 to BI?1 equals a sum of S and a sum from A1 to AI?1.

Abstract: According to an embodiment, a signal processing apparatus includes a first signal processor, a second signal processor and a third signal processor. The first signal processor suppresses an offset component remaining in a reproduction signal read from an optical recording medium to obtain a first signal. The second signal processor suppresses a nonlinear distortion component remaining in the first signal to obtain a second signal. The third signal processor suppresses a correlation noise component remaining in the second signal to obtain a third signal.