Patents by Inventor Kazuaki TAKESAKO

Kazuaki TAKESAKO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11018140
    Abstract: A semiconductor device and a manufacturing method of the same are provided. The method includes forming a plurality of first conductive structures and a first dielectric layer between the first conductive structures on a substrate. The method also includes forming a trench between the first dielectric layer and the first conductive structures. The method further includes forming a liner material on a sidewall and a bottom of the trench. In addition, the method includes forming a conductive plug on the liner material in the trench. The method also includes removing the liner material to form an air gap, and the air gap is located between the conductive plug and the first dielectric layer.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: May 25, 2021
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Yi-Hao Chien, Kazuaki Takesako, Kai Jen, Hung-Yu Wei
  • Patent number: 10910380
    Abstract: A method of manufacturing a DRAM includes isolation structures and word line sets are formed in the substrate. A conductive material is formed on the substrate. Conductive material is removed to form first openings in the conductive material. The first openings expose surfaces of the substrate in the first areas and divide the conductive material into conductive layers, thereby the conductive layers are located on surfaces of the substrate in the second areas. A first dielectric material is filled in the first openings so as to form first dielectric layers on the substrate in the first areas. Top surfaces of the conductive layers are lower than top surfaces of the first dielectric layers. Second dielectric layers are formed respectively in the conductive layers. Capacitors are formed respectively on the conductive posts.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: February 2, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Kazuaki Takesako, Huang-Nan Chen, Wei-Che Chang
  • Publication number: 20200335506
    Abstract: A semiconductor device and a manufacturing method of the same are provided. The method includes forming a plurality of first conductive structures and a first dielectric layer between the first conductive structures on a substrate. The method also includes forming a trench between the first dielectric layer and the first conductive structures. The method further includes forming a liner material on a sidewall and a bottom of the trench. In addition, the method includes forming a conductive plug on the liner material in the trench. The method also includes removing the liner material to form an air gap, and the air gap is located between the conductive plug and the first dielectric layer.
    Type: Application
    Filed: April 19, 2019
    Publication date: October 22, 2020
    Inventors: Yi-Hao CHIEN, Kazuaki TAKESAKO, Kai JEN, Hung-Yu WEI
  • Publication number: 20200286796
    Abstract: Provided is a semiconductor structure including a substrate, at least two tested structures, an isolation structure, and a short-circuit detection structure. At least two tested structures are disposed on the substrate. The at least two tested structures include a conductive material. The isolation structure is sandwiched between at least two tested structures. The detection structure includes a detecting layer, and the detecting layer is disposed on one of the at least two tested structures, so that a short circuit defect between the at least two tested structures may be identified in an electron beam detecting process, and the detecting layer includes a conductive material. A manufacturing method of the semiconductor structure and a method for detecting a short circuit of the semiconductor structure are also provided.
    Type: Application
    Filed: March 4, 2020
    Publication date: September 10, 2020
    Applicant: Winbond Electronics Corp.
    Inventors: Hung-Ming Su, Kazuaki Takesako, Chun-Chiao Tseng
  • Patent number: 10714482
    Abstract: A dynamic random access memory and a method of fabricating the same are provided. The dynamic random access memory includes forming a gate trench in a substrate. An isolation structure is formed in the substrate and defines a plurality of active regions arranged in a column in a first direction. A buried word line structure is formed to fill the gate trench and extend along the first direction and across the plurality of active regions and the isolation structure. A plurality of first fin structures is formed in an intersecting region of the plurality of active regions and the buried word line structure, arranged in a column along the first direction, and surrounded and covered by the buried word line structure. A dielectric layer is formed on the substrate to fill the gate trench and cover the buried word line structure.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: July 14, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Kazuaki Takesako, Kazutaka Manabe
  • Publication number: 20200212044
    Abstract: A dynamic random access memory and a method of fabricating the same are provided. The dynamic random access memory includes forming a gate trench in a substrate. An isolation structure is formed in the substrate and defines a plurality of active regions arranged in a column in a first direction. A buried word line structure is formed to fill the gate trench and extend along the first direction and across the plurality of active regions and the isolation structure. A plurality of first fin structures is formed in an intersecting region of the plurality of active regions and the buried word line structure, arranged in a column along the first direction, and surrounded and covered by the buried word line structure. A dielectric layer is formed on the substrate to fill the gate trench and cover the buried word line structure.
    Type: Application
    Filed: March 10, 2020
    Publication date: July 2, 2020
    Applicant: Winbond Electronics Corp.
    Inventors: Kazuaki Takesako, Kazutaka Manabe
  • Patent number: 10636796
    Abstract: A dynamic random access memory and a method of fabricating the same are provided. The dynamic random access memory includes a substrate, an isolation structure, a buried word line structure, and a plurality of a first fin structures. The isolation structure is disposed in the substrate and defines a plurality of active regions arranged in a column in a first direction. The buried word line structure is located in the substrate and extended along the first direction and across the plurality of active regions and the isolation structure. The plurality of first fin structures is located in an intersecting region of the plurality of active regions and the buried word line structure, arranged in a column along the first direction, and surrounded and covered by the buried word line structure.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: April 28, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Kazuaki Takesako, Kazutaka Manabe
  • Publication number: 20200119020
    Abstract: A method of manufacturing a DRAM includes isolation structures and word line sets are formed in the substrate. A conductive material is formed on the substrate. Conductive material is removed to form first openings in the conductive material. The first openings expose surfaces of the substrate in the first areas and divide the conductive material into conductive layers, thereby the conductive layers are located on surfaces of the substrate in the second areas. A first dielectric material is filled in the first openings so as to form first dielectric layers on the substrate in the first areas. Top surfaces of the conductive layers are lower than top surfaces of the first dielectric layers. Second dielectric layers are formed respectively in the conductive layers. Capacitors are formed respectively on the conductive posts.
    Type: Application
    Filed: December 17, 2019
    Publication date: April 16, 2020
    Applicant: Winbond Electronics Corp.
    Inventors: Kazuaki Takesako, Huang-Nan Chen, Wei-Che Chang
  • Patent number: 10217748
    Abstract: A dynamic random access memory (DRAM) includes a substrate, a bit line, a capacitor contact, a dielectric structure, a capacitor, and a landing pad. The bit line is located on the substrate. The capacitor contact is aside the bit line. The capacitor contact protrudes from a space between adjacent bit lines, such that upper sidewalls of the capacitor contact are exposed by the bit line. The dielectric structure is located on the upper surface of the bit line and extending to one portion of the upper sidewalls of the capacitor contacts. The capacitor is located above the capacitor contact. The landing pad is located between the capacitor contact and the capacitor. The landing pad at least covers one portion of the upper surface of the capacitor contact. A contact area between landing pad and the capacitor contact is greater than a contact area between the landing pad and the capacitor.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: February 26, 2019
    Assignee: Winbond Electronics Corp.
    Inventor: Kazuaki Takesako
  • Publication number: 20190043864
    Abstract: A dynamic random access memory and a method of fabricating the same are provided. The dynamic random access memory includes a substrate, an isolation structure, a buried word line structure, and a plurality of a first fin structures. The isolation structure is disposed in the substrate and defines a plurality of active regions arranged in a column in a first direction. The buried word line structure is located in the substrate and extended along the first direction and across the plurality of active regions and the isolation structure. The plurality of first fin structures is located in an intersecting region of the plurality of active regions and the buried word line structure, arranged in a column along the first direction, and surrounded and covered by the buried word line structure.
    Type: Application
    Filed: August 2, 2017
    Publication date: February 7, 2019
    Applicant: Winbond Electronics Corp.
    Inventors: Kazuaki Takesako, Kazutaka Manabe
  • Publication number: 20190019795
    Abstract: A dynamic random access memory (DRAM) includes a substrate, isolation structures, word line sets, bit-line structures, spacers, capacitors, and capacitor contacts. The isolation structures are located in the substrate to divide the substrate into active areas. The active areas are configured in the shape of band and arranged in an array. The word line sets are disposed in parallel in a Y direction in the substrate. The bit-line structures are disposed in parallel in an X direction on the substrate and cross the word line sets. The spacers are disposed in parallel in the X direction on sidewalls of the substrate, wherein the spacers include silicon oxide. The capacitors are respectively disposed at two terminals of the long side of each of the active areas. The capacitor contacts are respectively located between the capacitors and the active areas.
    Type: Application
    Filed: June 5, 2018
    Publication date: January 17, 2019
    Applicant: Winbond Electronics Corp.
    Inventors: Kazuaki Takesako, Huang-Nan Chen, Wei-Che Chang
  • Publication number: 20180342517
    Abstract: A dynamic random access memory (DRAM) includes a substrate, a bit line, a capacitor contact, a dielectric structure, a capacitor, and a landing pad. The bit line is located on the substrate. The capacitor contact is aside the bit line. The capacitor contact protrudes from a space between adjacent bit lines, such that upper sidewalls of the capacitor contact are exposed by the bit line. The dielectric structure is located on the upper surface of the bit line and extending to one portion of the upper sidewalls of the capacitor contacts. The capacitor is located above the capacitor contact. The landing pad is located between the capacitor contact and the capacitor. The landing pad at least covers one portion of the upper surface of the capacitor contact. A contact area between landing pad and the capacitor contact is greater than a contact area between the landing pad and the capacitor.
    Type: Application
    Filed: May 25, 2017
    Publication date: November 29, 2018
    Applicant: Winbond Electronics Corp.
    Inventor: Kazuaki Takesako
  • Patent number: 10083906
    Abstract: A memory device and a method for manufacturing a memory device are provided. The memory device includes a semiconductor substrate having a trench, an oxide layer formed on a surface of the trench, and a buried word line formed in the trench having the oxide layer formed thereon. The oxide layer includes a first portion extending downward from a top surface of the semiconductor substrate, a second portion extending upward from a bottom portion of the trench, and a third portion formed between and adjoining the first portion and the second portion. The third portion tapers toward the second portion. The first portion of the oxide layer is located between the buried word line and the surface of the trench.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: September 25, 2018
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Kai Jen, Wei-Che Chang, Kazutaka Manabe, Kazuaki Takesako, Noriaki Ikeda, Yoshinori Tanaka
  • Patent number: 10074654
    Abstract: Provided is a dynamic random access memory. A plurality of isolation structures is disposed in a substrate to define a plurality of active regions arranged along a first direction. The substrate has a trench extended along the first direction and passing through the plurality of isolation structures and the plurality of active regions. A buried word line is disposed in the trench. A plurality of gate dielectric layers is disposed in the trench of the plurality of active regions to surround and cover the buried word line. A cap layer covers the buried word line. The height of the top surface of the second side of the buried word line is lower than the height of the top surface of the first side of the buried word line passing through the plurality of active regions and the plurality of isolation structures.
    Type: Grant
    Filed: March 31, 2018
    Date of Patent: September 11, 2018
    Assignee: Winbond Electronics Corp.
    Inventors: Kazuaki Takesako, Kazutaka Manabe, Noriaki Ikeda, Wei-Che Chang
  • Patent number: 9972626
    Abstract: Provided is a dynamic random access memory. A plurality of isolation structures is disposed in a substrate to define a plurality of active regions arranged along a first direction. The substrate has a trench extended along the first direction and passing through the plurality of isolation structures and the plurality of active regions. A buried word line is disposed in the trench. A plurality of gate dielectric layers is disposed in the trench of the plurality of active regions to surround and cover the buried word line. A cap layer covers the buried word line. The height of the top surface of the second side of the buried word line is lower than the height of the top surface of the first side of the buried word line passing through the plurality of active regions and the plurality of isolation structures.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: May 15, 2018
    Assignee: Winbond Electronics Corp.
    Inventors: Kazuaki Takesako, Kazutaka Manabe, Noriaki Ikeda, Wei-Che Chang
  • Patent number: 9947669
    Abstract: A dynamic random access memory (DRAM) includes a substrate, a plurality of isolation structures, a plurality of conductive structure sets, a plurality of bit-line structures, and a plurality of spacers. The substrate has a plurality of active areas. The isolation structures are located in the substrate and extending along a first direction. Each of the isolation structures is disposed between two adjacent active areas. The conductive structure sets are disposed in parallel along the first direction and on the substrate. The bit-line structures are disposed in parallel along a second direction and on the substrate. The bit-line structures penetrate through the conductive structure sets. The spacers are disposed in parallel along the second direction and on sidewalls of the bit-line structures, so as to electrically isolate the bit-line structures from the conductive structure sets.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: April 17, 2018
    Assignee: Winbond Electronics Corp.
    Inventors: Kazuaki Takesako, Yoshinori Tanaka
  • Patent number: 9685448
    Abstract: Disclosed herein is a method includes: forming first and second cavities, the first cavity having a first width, each of the second cavities having a second width narrower than the first width; forming a first conductive layer buried in the second cavities and formed on bottom and side surface of the semiconductor substrate defined by the first cavity so that a third cavity is defined by the first conductive layer formed on the bottom and side surface of the semiconductor substrate; subjecting an etch back process to the first conductive layer so that a first conductive portion is formed at a bottom corner of the first cavity, further a fourth cavity is formed on the semiconductor substrate uncovered with the first conductive portion in the first cavity; and forming a first insulating layer in the fourth cavity and in the second cavity.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: June 20, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Kazuaki Takesako
  • Patent number: 9385112
    Abstract: A semiconductor device includes a substrate having laterally-adjacent first and second substrate regions. A first isolation region is at least in the first substrate region. An active region is at least in the second substrate region. The active region is laterally adjacent to the first isolation region. A conductive line extends from the first substrate region into the second substrate region. The conductive line is over the first isolation region and over the active region. A top surface of the conductive line over the first isolation region in the first substrate region is lower in the substrate than an elevationally outer surface of active material of the active region in the second substrate region. A top surface of the conductive line over the active region in the second substrate region is higher in the substrate than the elevationally outer surface of the active material of the active region in the second substrate region.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: July 5, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Kazuaki Takesako
  • Publication number: 20160163709
    Abstract: Disclosed herein is a method includes: forming first and second cavities, the first cavity having a first width, each of the second cavities having a second width narrower than the first width; forming a first conductive layer buried in the second cavities and formed on bottom and side surface of the semiconductor substrate defined by the first cavity so that a third cavity is defined by the first conductive layer formed on the bottom and side surface of the semiconductor substrate; subjecting an etch back process to the first conductive layer so that a first conductive portion is formed at a bottom corner of the first cavity, further a fourth cavity is formed on the semiconductor substrate uncovered with the first conductive portion in the first cavity; and forming a first insulating layer in the fourth cavity and in the second cavity.
    Type: Application
    Filed: February 2, 2016
    Publication date: June 9, 2016
    Inventor: Kazuaki Takesako
  • Patent number: 9269716
    Abstract: Disclosed herein is a method includes: forming first and second cavities, the first cavity having a first width, each of the second cavities having a second width narrower than the first width; forming a first conductive layer buried in the second cavities and formed on bottom and side surface of the semiconductor substrate defined by the first cavity so that a third cavity is defined by the first conductive layer formed on the bottom and side surface of the semiconductor substrate; subjecting an etch back process to the first conductive layer so that a first conductive portion is formed at a bottom corner of the first cavity, further a fourth cavity is formed on the semiconductor substrate uncovered with the first conductive portion in the first cavity; and forming a first insulating layer in the fourth cavity and in the second cavity.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: February 23, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Kazuaki Takesako