Patents by Inventor Kazuhide Kiuchi

Kazuhide Kiuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5213991
    Abstract: In a method of making a MOSFET-type semiconductor device of this invention, a surface of a semiconductor substrate is covered in a predetermined pattern with an insulating layer comprising a silicon-nitride-containing film or with an insulating layer whose top surface and side surfaces bear a silicon-nitride-containing film, thereby forming on the semiconductor substrate a recess region at which the semiconductor substrate is exposed. An epitaxial silicon film and polycrystalline silicon film are formed simultaneously on the exposed semiconductor substrate and on the insulating film, respectively. A whole channel region and a part of source and drain diffused-layer regions are formed in the epitaxial silicon film, and source and drain diffused-layer regions are formed in the polycrystalline silicon film. A gate electrode of this MOSFET-type semiconductor device may be formed at the recess region by a self-align method.
    Type: Grant
    Filed: March 24, 1992
    Date of Patent: May 25, 1993
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Hiroshi Inokawa, Toshio Kobayashi, Kazuhide Kiuchi
  • Patent number: 4894706
    Abstract: A chip carrying member (1) such as a film carrier carrying a chip (10) and elastic spacers (2, 3) are stacked to form an elementary unit with adjusting its thickness. By using an aligning aperture (12) of a thin sheet (1), a plurality of the elementary units are stacked to form a laminated structure. From a side surface of the laminated structure, leads (13) are extended to be connected to a wiring board (241), or after the leads (13) are buried in an insulator (8), the leads (13) and insulator (8) are abraded to form a coplanar surface and then a wiring layer (82) for interconnecting is formed on the abraded surface. A usual chip can be mounted on the chip carrying member (1) without any work with a high accuracy in alignment of the lamination and furthermore with a high accuracy in a lamination pitch of the chip carrying member (1), so that the leads (13) of the chip (10) can be wired precisely and finely. A low cost and high density three-dimensional packaging structure can be realized.
    Type: Grant
    Filed: October 9, 1986
    Date of Patent: January 16, 1990
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Yoshiyuki Sato, Kazuhide Kiuchi, Junji Watanabe, Kunio Koyabu, Masanobu Oohata, Katsuhiko Aoki
  • Patent number: 4538167
    Abstract: The semiconductor device relates to a shorted junction type programmable read only memory semiconductor device. The memory consists of a semiconductor region including a PN junction or a Schottky junction and a control electrode coupled to the junction. The junction is destroyed or shorted by causing a field or carrier injection effect in the semiconductor region with a voltage impressed on the control electrode.
    Type: Grant
    Filed: September 8, 1981
    Date of Patent: August 27, 1985
    Assignee: Nippon Telegraph & Telephone Public Corporation
    Inventors: Hideo Yoshino, Eisuke Arai, Kazuhide Kiuchi