Abstract: Apparatuses and methods for controlling word lines and sense amplifiers in a semiconductor device are described. An example apparatus includes: a sub word line selection signal decoder which activates at least one of a plurality of sub word selection signals responsive to row address signals; a column segment selection signal decoder which activates at least one of a plurality of column segment signals responsive to a portion of column address signals and a portion of the row address signals; a column segment selection circuit which activates at least one of a plurality of column-subword selection signals responsive to the activated column segment signal and the activated sub word selection signal; and a sub word line driver which activates at least one of a plurality of sub word lines responsive to an activated main word line and the activated sub word selection signal.

Abstract: A device with error correction is provided. The device includes a plurality of memory cells, and reference read write circuit, a plurality of sense amplifiers, and an error-correction code control block. The reference read write circuit is configured to generate a reference voltage in response to data stored in at least one of the plurality of memory cells. A plurality of sense amplifiers are each coupled to a respective memory cell of the plurality of memory cells. An error-correction code (ECC) control block may output an error signal when the ECC control block detects that it is unable to correct error data in one or more respective memory cells. The reference read write circuit may overwrite data in the at least one of the plurality of memory cells in response to the error signal.

Abstract: A device with error correction is provided. The device includes a plurality of memory cells, and reference read write circuit, a plurality of sense amplifiers, and an error-correction code control block. The reference read write circuit is configured to generate a reference voltage in response to data stored in at least one of the plurality of memory cells. A plurality of sense amplifiers are each coupled to a respective memory cell of the plurality of memory cells. An error-correction code (ECC) control block may output an error signal when the ECC control block detects that it is unable to correct error data in one or more respective memory cells. The reference read write circuit may overwrite data in the at least one of the plurality of memory cells in response to the error signal.

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. One method includes determining whether to access a first memory cell of a first memory cell array or a second memory cell of a second memory cell array, where a first digit line coupled to the first memory cell is coupled to a paging buffer register including a sense amplifier. The method further includes operating a transfer gate based at least in part on determining to read the second memory cell of the second memory cell array, where the transfer gate is configured to selectively couple a second digit line coupled to the second memory cell to the paging buffer register through the first digit line.

Abstract: Methods, systems, and devices for operating a memory device are described. One method includes caching data of a memory cell at a sense amplifier of a row buffer upon performing a first read of the memory cell; determining to perform at least a second read of the memory cell after performing the first read of the memory cell; and reading the data of the memory cell from the sense amplifier for at least the second read of the memory cell.

Abstract: Apparatuses and methods for controlling word lines and sense amplifiers in a semiconductor device are described. An example apparatus includes: a sub word line selection signal decoder which activates at least one of a plurality of sub word selection signals responsive to row address signals; a column segment selection signal decoder which activates at least one of a plurality of column segment signals responsive to a portion of column address signals and a portion of the row address signals; a column segment selection circuit which activates at least one of a plurality of column-subword selection signals responsive to the activated column segment signal and the activated sub word selection signal; and a sub word line driver which activates at least one of a plurality of sub word lines responsive to an activated main word line and the activated sub word selection signal.

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. One method includes determining whether to access a first memory cell of a first memory cell array or a second memory cell of a second memory cell array, where a first digit line coupled to the first memory cell is coupled to a paging buffer register including a sense amplifier. The method further includes operating a transfer gate based at least in part on determining to read the second memory cell of the second memory cell array, where the transfer gate is configured to selectively couple a second digit line coupled to the second memory cell to the paging buffer register through the first digit line.

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. One method includes determining whether to access a first memory cell of a first memory cell array or a second memory cell of a second memory cell array, where a first digit line coupled to the first memory cell is coupled to a paging buffer register including a sense amplifier. The method further includes operating a transfer gate based at least in part on determining to read the second memory cell of the second memory cell array, where the transfer gate is configured to selectively couple a second digit line coupled to the second memory cell to the paging buffer register through the first digit line.

Abstract: A device with error correction is provided. The device includes a plurality of memory cells, and reference read write circuit, a plurality of sense amplifiers, and an error-correction code control block. The reference read write circuit is configured to generate a reference voltage in response to data stored in at least one of the plurality of memory cells. A plurality of sense amplifiers are each coupled to a respective memory cell of the plurality of memory cells. An error-correction code (ECC) control block may output an error signal when the ECC control block detects that it is unable to correct error data in one or more respective memory cells. The reference read write circuit may overwrite data in the at least one of the plurality of memory cells in response to the error signal.

Abstract: A semiconductor device includes first and second memory cell arrays, each including a plurality of memory cells, each of which is connected between first and second terminals and is configured to be written to a first resistance state by applying a first current in a first direction between the first and second terminals and be written to a second resistance state by applying a second current in a second direction opposite to the first direction between the first and second terminals. The semiconductor device further includes an error-correction circuit and a control circuit. Additional apparatus and methods are disclosed.

Abstract: Apparatuses and methods for controlling word lines and sense amplifiers in a semiconductor device are described. An example apparatus includes: a sub word line selection signal decoder which activates at least one of a plurality of sub word selection signals responsive to row address signals; a column segment selection signal decoder which activates at least one of a plurality of column segment signals responsive to a portion of column address signals and a portion of the row address signals; a column segment selection circuit which activates at least one of a plurality of column-subword selection signals responsive to the activated column segment signal and the activated sub word selection signal; and a sub word line driver which activates at least one of a plurality of sub word lines responsive to an activated main word line and the activated sub word selection signal.

Abstract: A device is provided with: memory cell array including plurality of first and second memory cells and one or more third memory cells; judging circuit that judges plurality of data values held by selected first and second memory cells of the first and second memory cells, by referring to reference potential corresponding to reference data held by a selected third memory cell; and error detection and correction circuit that detects whether or not there is error in the judged data values of the first and/or second memory cells, with judged data value of the first and second memory cells as error correcting code. When the error detection and correction circuit detects that there is error exceeding error correction capability in the judged data values, control is performed to write reference data to the selected third memory cell.

Abstract: A semiconductor device is disclosed in which there are provided a first substrate including memory cells and at least one bit line electrically coupled to the memory cells, and a second substrate including a sense amplifier. Each of the memory cells includes a first transistor, and the sense amplifier includes a second transistor. The second substrate is stacked with the first substrate such that the sense amplifier amplifies data transferred through the bit line from a selected one of the memory cells. The first transistor is lower in carrier mobility than the second transistor.

Abstract: Disclosed herein is a device that includes a memory cell array including plurality of word lines, a plurality of bit lines each intersecting the word lines and a plurality of memory cells each disposed at an associated one of intersections of the word and bit lines, and the device further includes a driver configured to drive a selected one of the word lines from an inactive level to an active and to drive the selected one of the word lines from the active level to an intermediate level at a first rate and from the intermediated level to the inactive level at a second rate. The intermediate level is between the active and inactive levels, and the first rate is greater than the second rate.

Abstract: A semiconductor includes a plurality of memory cell arrays each of which includes a plurality of memory cells. Bitlines extend in one direction in the memory cell arrays to transfer data stored in the memory cells. Wordlines extend perpendicular to the bitlines in the memory cell arrays to select at least one of the memory cells. Local data lines extend parallel to the wordlines outside of the memory cell arrays and convey signals from bitlines. Global data lines convey signals from the local data lines. The global data lines include a part extending parallel to the wordlines and the part is disposed over another one of the memory cell arrays other than a selected memory cell array.

Abstract: A method includes measuring a first pulse width of a resistance variable memory cell coupled between a first terminal and a second terminal, the first pulse width including a period from starting a first data writing of the resistance variable memory cell by applying a voltage between the first and second terminals to ending the first data writing of the resistance variable memory cell, and measuring a second pulse width of the resistance variable memory cell coupled between the first and the second terminal. The method includes setting longer one of the first and second pulse widths in a first storage area as a pulse width to be used in program.

Abstract: Disclosed herein is a device that includes: a memory cell array including a plurality of memory cells, the memory cell array operates on a first internal voltage; a peripheral circuit accessing selected one or ones of the memory cells, the peripheral circuit operates on a second internal voltage; a first internal voltage generation circuit that supplies the first internal voltage to the memory cell array; and a second internal voltage generation circuit that supplies the second internal voltage to the peripheral circuit. The second internal voltage generation circuit sets the second internal voltage to a first voltage value in a first mode, and to a second voltage value that is different from the first voltage value in a second mode. The first internal voltage generation circuit sets the first internal voltage to a third voltage value in both the first and second modes.

Abstract: Disclosed herein a device that includes a memory cell array including plurality of word lines, a plurality of bit lines each intersecting the word lines and a plurality of memory cells each disposed at an associated one of intersections of the word and bit lines, and the device further includes a driver configured to drive a selected one of the word lines from an inactive level to an active and to drive the selected one of the word lines from the active level to an intermediate level at a first rate and from the intermediated level to the inactive level at a second rate. The intermediate level is between the active and inactive levels, and the first rate is greater than the second rate.

Abstract: A semiconductor device comprises a memory cell, a bit line, a sense amplifier operating between a first voltage and a second voltage higher than the first voltage, a transfer control circuit including a transfer transistor, and a write circuit writing data into the memory cell through the bit line based on the first voltage and a third voltage. The sense amplifier receives and amplifiers the signal voltage at a sense node when the transfer transistor controls the connection between the bit line and the sense node in response to a transfer control voltage. The third voltage is set to a voltage lower than the second voltage and higher than the transfer control voltage, and the sense node is set to a voltage higher than the transfer control voltage in an initial period of a read operation before the data of the memory cell is read out to the bit line.

Abstract: A semiconductor device has a DRAM cell configured from an information charge accumulating capacitor and a memory cell selecting transistor, the threshold voltage value of a MOS transistor that constitutes a sense circuit is monitored, and the monitored threshold voltage value of the MOS transistor is converted through the use of a transfer ratio that is determined based on the capacitance of the information charge accumulating capacitor and the parasitic capacitance of the bit line. The converted voltage value is level-shifted so that the pre-charge voltage of a pre-charge circuit is a pre-set voltage, a current feeding capability is added to the level-shifted voltage value, and the voltage is fed as the pre-charge voltage.