Patents by Inventor Kazuhiko Kashima

Kazuhiko Kashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10766077
    Abstract: The holder has a first surface and a second surface. The head includes a cutting edge portion and a shank portion. The holder is provided with a first hole and a second hole communicating with the first hole, the first hole extending in a third direction inclined by a second angle relative to a second direction extending from the second surface toward the first surface when viewed in a direction parallel to the axis line. The shank portion has a flat surface portion, and is provided inside the second hole. The fastening portion is provided inside the first hole, and is in contact with the flat surface portion. In a plane perpendicular to the axis line, a third angle between the second direction and a fourth direction perpendicular to the flat surface portion is larger than the second angle. The third angle is less than 90°.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: September 8, 2020
    Assignee: Sumitomo Electric Hardmetal Corp.
    Inventors: Yoshikatsu Mori, Kouki Matsubara, Ryusei Hamada, Masaaki Jindai, Kazuhiko Kashima, Yasuhiro Kajiwara
  • Publication number: 20190232388
    Abstract: The holder has a first surface and a second surface. The head includes a cutting edge portion and a shank portion. The holder is provided with a first hole and a second hole communicating with the first hole, the first hole extending in a third direction inclined by a second angle relative to a second direction extending from the second surface toward the first surface when viewed in a direction parallel to the axis line. The shank portion has a flat surface portion, and is provided inside the second hole. The fastening portion is provided inside the first hole, and is in contact with the flat surface portion. In a plane perpendicular to the axis line, a third angle between the second direction and a fourth direction perpendicular to the flat surface portion is larger than the second angle. The third angle is less than 90°.
    Type: Application
    Filed: February 27, 2017
    Publication date: August 1, 2019
    Applicants: SUMITOMO ELECTRIC HARDMETAL CORP., SUMITOMO ELECTRIC HARDMETAL CORP.
    Inventors: Yoshikatsu Mori, Kouki Matsubara, Ryusei Hamada, Masaaki Jindai, Kazuhiko Kashima, Yasuhiro Kajiwara
  • Patent number: 9541452
    Abstract: According to an embodiment, a method of forming a calibration curve is provided. The method includes ion-implanting different doses of an impurity into a plurality of first samples, measuring an intensity of photoluminescence deriving from the impurity by a photoluminescence spectroscopy for the first samples and a second sample made of the same semiconductor. Based on the amount of implanted impurity, the intensity of the photoluminescence, and a concentration of the impurity contained in the second sample measured by a method other than the photoluminescence spectroscopy, a calibration curve is formed.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: January 10, 2017
    Assignee: GlobalWafers Japan Co., Ltd.
    Inventors: Satoko Nakagawa, Kazuhiko Kashima
  • Publication number: 20150338276
    Abstract: According to an embodiment, a method of forming a calibration curve is provided. The method includes ion-implanting different doses of an impurity into a plurality of first samples, measuring an intensity of photoluminescence deriving from the impurity by a photoluminescence spectroscopy for the first samples and a second sample made of the same semiconductor. Based on the amount of implanted impurity, the intensity of the photoluminescence, and a concentration of the impurity contained in the second sample measured by a method other than the photoluminescence spectroscopy, a calibration curve is formed.
    Type: Application
    Filed: May 22, 2015
    Publication date: November 26, 2015
    Inventors: Satoko NAKAGAWA, Kazuhiko KASHIMA
  • Patent number: 8999864
    Abstract: A silicon wafer for preventing a void defect in a bulk region from becoming source of contamination and slip generation in a device process is provided. And a heat-treating method thereof for reducing crystal defects such as COP in a region near the wafer surface to be a device active region is provided. The silicon wafer has a surface region 1 which is a defect-free region and a bulk region 2 including void defect of a polyhedron whose basic shape is an octahedron in which a corner portion of the polyhedron is in the curved shape and an inner-wall oxide film the void defect is removed. The silicon wafer is provided by performing a heat-treating method in which gas to be supplied, inner pressure of spaces and a maximum achievable temperature are set to a predetermined value when subjecting the silicon wafer produced by a CZ method to RTP.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: April 7, 2015
    Assignee: Global Wafers Japan Co., Ltd.
    Inventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima, Hiroyuki Saito
  • Publication number: 20150017086
    Abstract: A silicon single crystal manufacturing method includes: applying a transverse magnetic field to a melt of polysilicon with a carbon concentration of at most 1.0×1015 atoms/cm3 as a raw material; rotating the crucible at 5.0 rpm or less; allowing inert gas to flow at rate A (m/sec) of formula (1) at a position 20-50% of Y above the melt surface; controlling the rate A within the range of 0.2 to 5,000/d (m/sec) (d: crystal diameter (mm)); and reducing the total power of side and bottom heaters by 3 to 30% and the side heater power by 5 to 45% until the solidified fraction reaches 30%.
    Type: Application
    Filed: July 10, 2014
    Publication date: January 15, 2015
    Applicant: GLOBALWAFERS JAPAN CO., LTD.
    Inventors: Yuta NAGAI, Satoko Nakagawa, Kazuhiko Kashima
  • Patent number: 8476149
    Abstract: A silicon wafer produced from a silicon single crystal ingot grown by Czochralski process is subjected to rapid heating/cooling thermal process at a maximum temperature (T1) of 1300° C. or more, but less than 1380° C. in an oxidizing gas atmosphere having an oxygen partial pressure of 20% or more, but less than 100%. The silicon wafer according to the invention has, in a defect-free region (DZ layer) including at least a device active region of the silicon wafer, a high oxygen concentration region having a concentration of oxygen solid solution of 0.7×1018 atoms/cm3 or more and at the same time, the defect-free region contains interstitial silicon in supersaturated state.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: July 2, 2013
    Assignee: Global Wafers Japan Co., Ltd.
    Inventors: Hiromichi Isogai, Takeshi Senda, Eiji Toyoda, Kumiko Murayama, Koji Izunome, Susumu Maeda, Kazuhiko Kashima, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Yoichiro Mochizuki, Akihiko Kobayashi, Senlin Fu
  • Patent number: 8399341
    Abstract: The invention is to provide a method for heat treating a silicon wafer reducing grown-in defects while suppressing generation of slip during RTP and improving surface roughness of the wafer. The method performing a first heat treatment while introducing a rare gas, the first heat treatment comprising the steps of rapidly heating the wafer to T1 of 1300° C. or higher and the melting point of silicon or lower, keeping the wafer at T1, rapidly cooling the wafer to T2 of 400-800° C. and keeping the wafer at T2; and performing a second heat treatment while introducing an oxygen gas in an amount of 20-100 vol. %, the second heat treatment comprising the steps of keeping the wafer at T2, rapidly heating the wafer from T2 to T3 of 1250° C. or higher and the melting point of silicon or lower, keeping the wafer at T3 and rapidly cooling the wafer.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: March 19, 2013
    Assignee: Covalent Materials Corporation
    Inventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Kumiko Murayama, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima
  • Patent number: 8252700
    Abstract: In a method of heat treating a wafer obtained by slicing a silicon single crystal ingot manufactured by the Czochralski method, a rapid heating/cooling heat treatment is carried out by setting a holding time at an ultimate temperature of 1200° C. or more and a melting point of silicon or less to be equal to or longer than one second and to be equal to or shorter than 60 seconds in a mixed gas atmosphere containing oxygen having an oxygen partial pressure of 1.0% or more and 20% or less and argon, and an oxide film having a thickness of 9.1 nm or less or 24.3 nm or more is thus formed on a surface of the silicon wafer.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: August 28, 2012
    Assignee: Covalent Materials Corporation
    Inventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Kumiko Murayama, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima
  • Publication number: 20120184091
    Abstract: The invention is to provide a method for heat treating a silicon wafer reducing grown-in defects while suppressing generation of slip during RTP and improving surface roughness of the wafer. The method performing a first heat treatment while introducing a rare gas, the first heat treatment comprising the steps of rapidly heating the wafer to T1 of 1300° C. or higher and the melting point of silicon or lower, keeping the wafer at T1, rapidly cooling the wafer to T2 of 400-800° C. and keeping the wafer at T2; and performing a second heat treatment while introducing an oxygen gas in an amount of 20-100 vol. %, the second heat treatment comprising the steps of keeping the wafer at T2, rapidly heating the wafer from T2 to T3 of 1250° C. or higher and the melting point of silicon or lower, keeping the wafer at T3 and rapidly cooling the wafer.
    Type: Application
    Filed: May 17, 2010
    Publication date: July 19, 2012
    Applicant: Covalent Materials Corporation
    Inventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Kumiko Murayama, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima
  • Publication number: 20120139088
    Abstract: A silicon wafer for preventing a void defect in a bulk region from becoming source of contamination and slip generation in a device process is provided. And a heat-treating method thereof for reducing crystal defects such as COP in a region near the wafer surface to be a device active region is provided. The silicon wafer has a surface region 1 which is a defect-free region and a bulk region 2 including void defect of a polyhedron whose basic shape is an octahedron in which a corner portion of the polyhedron is in the curved shape and an inner-wall oxide film the void defect is removed. The silicon wafer is provided by performing a heat-treating method in which gas to be supplied, inner pressure of spaces and a maximum achievable temperature are set to a predetermined value when subjecting the silicon wafer produced by a CZ method to RTP.
    Type: Application
    Filed: May 28, 2010
    Publication date: June 7, 2012
    Applicant: Covalent Materials Corporation
    Inventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima, Hiroyuki Saito
  • Patent number: 7977219
    Abstract: In a manufacturing method for a silicon wafer, a first heat treatment process is performed on the silicon wafer while introducing a first gas having an oxygen gas in an amount of 0.01 vol. % or more and 1.00 vol. % or less and a rare gas, and a second heat treatment process is performed while stopping introducing the first gas and introducing a second gas having an oxygen gas in an amount of 20 vol. % or more and 100 vol. % or less and a rare gas. In the first heat treatment process, the silicon wafer is rapidly heated to first temperature of 1300° C. or higher and a melting point of silicon or lower at a first heating rate, and kept at the first temperature. In the second heat treatment process, the silicon wafer is kept at the first temperature, and rapidly cooled from the first temperature at a first cooling rate.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: July 12, 2011
    Assignee: Covalent Materials Corporation
    Inventors: Hiromichi Isogai, Takeshi Senda, Eiji Toyoda, Kumiko Murayama, Koji Izunome, Susumu Maeda, Kazuhiko Kashima
  • Patent number: 7835604
    Abstract: The present invention provides a fiber Bragg grating element which is simply configured and capable of obtaining a high cut-off amount exceeding 40 dB in a wide range. A fiber Bragg grating element of the present invention has a plurality of gratings formed in an optical waveguide having a core and a cladding around the core thereby to perform high rejection filtering on an input optical signal over a desired bandwidth˜ the gratings being formed with a grating pitch between adjacent two of the gratings increasing toward a center in a longitudinal direction of the optical waveguide.
    Type: Grant
    Filed: February 16, 2006
    Date of Patent: November 16, 2010
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Yasuo Uemura, Kazuhiko Kashima, Toshiyuki Inukai
  • Publication number: 20100197146
    Abstract: In a method of heat treating a wafer obtained by slicing a silicon single crystal ingot manufactured by the Czochralski method, a rapid heating/cooling heat treatment is carried out by setting a holding time at an ultimate temperature of 1200° C. or more and a melting point of silicon or less to be equal to or longer than one second and to be equal to or shorter than 60 seconds in a mixed gas atmosphere containing oxygen having an oxygen partial pressure of 1.0% or more and 20% or less and argon, and an oxide film having a thickness of 9.1 nm or less or 24.3 nm or more is thus formed on a surface of the silicon wafer.
    Type: Application
    Filed: January 21, 2010
    Publication date: August 5, 2010
    Applicant: COVALENT MATERIALS CORPORATION
    Inventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Kumiko Murayama, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima
  • Publication number: 20100055884
    Abstract: In a manufacturing method for a silicon wafer, a first heat treatment process is performed on the silicon wafer while introducing a first gas having an oxygen gas in an amount of 0.01 vol. % or more and 1.00 vol. % or less and a rare gas, and a second heat treatment process is performed while stopping introducing the first gas and introducing a second gas having an oxygen gas in an amount of 20 vol. % or more and 100 vol. % or less and a rare gas. In the first heat treatment process, the silicon wafer is rapidly heated to first temperature of 1300° C. or higher and a melting point of silicon or lower at a first heating rate, and kept at the first temperature. In the second heat treatment process, the silicon wafer is kept at the first temperature, and rapidly cooled from the first temperature at a first cooling rate.
    Type: Application
    Filed: July 30, 2009
    Publication date: March 4, 2010
    Inventors: Hiromichi Isogai, Takeshi Senda, Eiji Toyoda, Kumiko Murayama, Koji Izunome, Susumu Maeda, Kazuhiko Kashima
  • Publication number: 20100038757
    Abstract: A silicon wafer produced from a silicon single crystal ingot grown by Czochralski process is subjected to rapid heating/cooling thermal process at a maximum temperature (T1) of 1300° C. or more, but less than 1380° C. in an oxidizing gas atmosphere having an oxygen partial pressure of 20% or more, but less than 100%. The silicon wafer according to the invention has, in a defect-free region (DZ layer) including at least a device active region of the silicon wafer, a high oxygen concentration region having a concentration of oxygen solid solution of 0.7×1018 atoms/cm3 or more and at the same time, the defect-free region contains interstitial silicon in supersaturated state.
    Type: Application
    Filed: July 30, 2009
    Publication date: February 18, 2010
    Inventors: Hiromichi Isogai, Takeshi Senda, Eiji Toyoda, Kumiko Murayama, Koji Izunome, Susumu Maeda, Kazuhiko Kashima, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Yoichiro Mochizuki, Akihiko Kobayashi, Senlin Fu
  • Patent number: 7591209
    Abstract: An object is to provide a vibration suppressing cutting tool which is inexpensive and can damp chattering extremely effectively, and which is simple in structure and is applicable to a wide variety of machining diameters and cutting conditions. The shank 2 of the holder 1 is formed with a pocket 4. In the pocket 4, a vibration suppressing piece 5 is received so as to be movable relative to the holder 1 and not protrudable from the pocket 4. Under kinetic energy from the holder during cutting, the vibration suppressing piece 5 alternately knocks against a pair of opposed inner wall surfaces 4a and 4b of the pocket along its surface, along a plurality of lines or on a plurality of points when the holder vibrates during cutting, thereby damping vibrations of the holder.
    Type: Grant
    Filed: November 26, 2004
    Date of Patent: September 22, 2009
    Assignee: Sumitomo Electric Hardmetal Corp.
    Inventors: Daisuke Murakami, Masanobu Ueda, Kazuhiko Kashima, Junya Okida, Norihide Kimura
  • Publication number: 20090052828
    Abstract: The present invention provides a fiber Bragg grating element which is simply configured and capable of obtaining a high cut-off amount exceeding 40 dB in a wide range. A fiber Bragg grating element of the present invention has a plurality of gratings formed in an optical waveguide having a core and a cladding around the core thereby to perform high rejection filtering on an input optical signal over a desired bandwidth, the gratings being formed with a grating pitch between adjacent two of the gratings increasing toward a center in a longitudinal direction of the optical waveguide.
    Type: Application
    Filed: February 16, 2006
    Publication date: February 26, 2009
    Applicant: THE FURUKAWA ELECTRIC CO., LTD.
    Inventors: Yasuo Uemura, Kazuhiko Kashima, Toshiyuki Inukai
  • Publication number: 20080277768
    Abstract: There is provided a silicon member that can prevent the resistivity of a member itself from varying in a semiconductor manufacturing process, in particular, in a plasma processing process, thereby making wafer processing uniform and being not an impurity contamination source to a wafer to be processed, and a method for manufacturing the same. The silicon member having a resistivity of 0.1 ?·cm or more and 100 ?·cm or less is manufactured with steps which are manufacturing a P-type silicon single crystal doped with 13 group atoms of a periodic table having an intrinsic resistivity of 1 ?·cm or more and 100 ?·cm or less, and changing said P-type silicon single crystal into an N-type silicon single crystal by oxygen donors formed by annealing at a temperature of 300° C. or more and 500° C. or less.
    Type: Application
    Filed: July 14, 2008
    Publication date: November 13, 2008
    Inventors: Masataka MORIYA, Kazuhiko Kashima, Shinichi Miyano
  • Publication number: 20080212925
    Abstract: The present invention provides an optical fiber for a fiber Bragg grating having a high reliability and superior performance. An optical fiber according to the present invention has a glass film containing micro porous bodies formed on the circumference of the optical fiber having a photosensitive core or both of the photosensitive core and a cladding.
    Type: Application
    Filed: December 26, 2007
    Publication date: September 4, 2008
    Applicant: THE FURUKAWA ELECTRIC CO., LTD.
    Inventors: Yoshihiro ARASHITANI, Kazuhiko Kashima, Yasuo Uemura, Mitsunori Okada