Patents by Inventor Kazuhiko Kashima

Kazuhiko Kashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070240628
    Abstract: Provided is a silicon wafer suitable for manufacturing a semiconductor device having a shallow junction. A silicon wafer wherein, in a region at a depth of less than 50 ?m from a surface, a density of oxygen deposition materials each having a diameter of not less than 10 nm is not more than 1×108/cm3. A silicon wafer for a semiconductor device, which is manufactured by applying heat treatment at a heat treatment temperature of not less than 1000° C. for heat treatment time of not more than 3 msec, wherein, in a region at a depth of less than 50 ?m from a surface, a density of oxygen deposition materials each having a diameter of not less than 10 nm is not more than 1×108/cm3.
    Type: Application
    Filed: April 5, 2007
    Publication date: October 18, 2007
    Applicant: Toshiba Ceramics Co., Ltd
    Inventors: Takashi Watanabe, Hiroyuki Saito, Takeshi Senda, Koji Izunome, Kazuhiko Kashima
  • Publication number: 20070227440
    Abstract: Silicon single crystal is pulled by the Czochralski method, using an As dopant comprising a mixed sintered compact of arsenic and silicon, the molar ratio of silicon being not smaller than 35% and not greater than 55% relative to arsenic.
    Type: Application
    Filed: June 1, 2007
    Publication date: October 4, 2007
    Inventor: Kazuhiko KASHIMA
  • Publication number: 20070089574
    Abstract: An object is to provide a vibration suppressing cutting tool which is inexpensive and can damp chattering extremely effectively, and which is simple in structure and is applicable to a wide variety of machining diameters and cutting conditions. The shank 2 of the holder 1 is formed with a pocket 4. In the pocket 4, a vibration suppressing piece 5 is received so as to be movable relative to the holder 1 and not protrudable from the pocket 4. Under kinetic energy from the holder during cutting, the vibration suppressing piece 5 alternately knocks against a pair of opposed inner wall surfaces 4a and 4b of the pocket along its surface, along a plurality of lines or on a plurality of points when the holder vibrates during cutting, thereby damping vibrations of the holder.
    Type: Application
    Filed: November 26, 2004
    Publication date: April 26, 2007
    Inventors: Daisuke Murakami, Masanobu Ueda, Kazuhiko Kashima, Junya Okida, Norihide Kimura
  • Publication number: 20070068447
    Abstract: In order to control a crystal defective area, to inhibit slip generation at the time of annealing treatment, and to manufacture a high quality silicon wafer of high strength with sufficient yields, a method of manufacturing a silicon wafer is provided in which a silicon single crystal is grown by way of Czochralski method under conditions where an oxygen concentration is 0.9×1018 atoms/cm3 or more and an oxidization induced stacking fault density is the maximum in an area within 20 mm of a wafer circumference, and an as-grown defect density of the wafer obtained by slicing the silicon single crystal is 1×107/cm3 or more over the whole region of the wafer.
    Type: Application
    Filed: September 26, 2006
    Publication date: March 29, 2007
    Inventors: Koji Izunome, Yumiko Hirano, Takashi Watanabe, Kazuhiko Kashima, Hiroyuki Saito, Takeshi Senda
  • Patent number: 7193294
    Abstract: A semiconductor substrate includes a support substrate 1 has gettering sites 10 for gettering impurity metal, an embedded insulating film 2 which is provided on the support substrate 1 and contains oxides of an element whose single bond energy to oxygen is higher than that to silicon, and a semiconductor layer (an SOI layer) 3 provided on the embedded insulating film 2.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: March 20, 2007
    Assignee: Toshiba Ceramics Co., Ltd.
    Inventors: Reiko Yoshimura, Tsukasa Tada, Koji Izunome, Kazuhiko Kashima
  • Publication number: 20060170078
    Abstract: There is provided a silicon member that can prevent the resistivity of a member itself from varying in a semiconductor manufacturing process, in particular, in a plasma processing process, thereby making wafer processing uniform and being not an impurity contamination source to a wafer to be processed, and a method for manufacturing the same. The silicon member having a resistivity of 0.1 ?·cm or more and 100 ?·cm or less is manufactured with steps which are manufacturing a P-type silicon single crystal doped with 13 group atoms of a periodic table having an intrinsic resistivity of 1 ?·cm or more and 100 ?·cm or less, and changing said P-type silicon single crystal into an N-type silicon single crystal by oxygen donors formed by annealing at a temperature of 300° C. or more and 500° C. or less.
    Type: Application
    Filed: January 26, 2006
    Publication date: August 3, 2006
    Inventors: Masataka Moriya, Kazuhiko Kashima, Shinichi Miyano
  • Publication number: 20060118868
    Abstract: A semiconductor substrate includes a support substrate 1 has gettering sites 10 for gettering impurity metal, an embedded insulating film 2 which is provided on the support substrate 1 and contains oxides of an element whose single bond energy to oxygen is higher than that to silicon, and a semiconductor layer (an SOI layer) 3 provided on the embedded insulating film 2.
    Type: Application
    Filed: December 3, 2004
    Publication date: June 8, 2006
    Inventors: Reiko Yoshimura, Tsukasa Tada, Koji Izunome, Kazuhiko Kashima
  • Patent number: 7048796
    Abstract: At the time of fabricating a silicon single crystal wafer from a nitrogen-doped silicon single crystal grown according to the Czochralski method, a silicon single crystal wafer covered with a region in which an oxygen precipitation bulk micro defect and an oxidation induced stacking fault mixedly exist is subjected to heat treatment at a temperature of 1100 to 1300° C. in a reducing gas or inert gas atmosphere. In such a manner, a method of fabricating a high-quality silicon single crystal wafer and a silicon single crystal wafer in which no grown-in crystal defects exist in the whole surface and oxygen precipitation bulk micro defects (BMD) are formed at a sufficiently high density to display the IG effect on the inner side can be provided. The single crystal wafer can be suitably used to form an operation region of a semiconductor device.
    Type: Grant
    Filed: September 16, 2004
    Date of Patent: May 23, 2006
    Assignee: Toshiba Ceramics Co., Ltd.
    Inventors: Masayuki Watanabe, Junichi Osanai, Akihiko Kobayashi, Kazuhiko Kashima, Hiroyuki Fujimori
  • Publication number: 20050215057
    Abstract: Silicon single crystal is pulled by the Czochralski method, using an As dopant comprising a mixed sintered compact of arsenic and silicon, the molar ratio of silicon being not smaller than 35% and not greater than 55% relative to arsenic.
    Type: Application
    Filed: March 22, 2005
    Publication date: September 29, 2005
    Inventor: Kazuhiko Kashima
  • Publication number: 20050039671
    Abstract: At the time of fabricating a silicon single crystal wafer from a nitrogen-doped silicon single crystal grown according to the Czochralski method, a silicon single crystal wafer covered with a region in which an oxygen precipitation bulk micro defect and an oxidation induced stacking fault mixedly exist is subjected to heat treatment at a temperature of 1100 to 1300° C. in a reducing gas or inert gas atmosphere. In such a manner, a method of fabricating a high-quality silicon single crystal wafer and a silicon single crystal wafer in which no grown-in crystal defects exist in the whole surface and oxygen precipitation bulk micro defects (BMD) are formed at a sufficiently high density to display the IG effect on the inner side can be provided. The single crystal wafer can be suitably used to form an operation region of a semiconductor device.
    Type: Application
    Filed: September 16, 2004
    Publication date: February 24, 2005
    Inventors: Masayuki Watanabe, Junichi Osanai, Akihiko Kobayashi, Kazuhiko Kashima, Hiroyuki Fujimori
  • Publication number: 20030029375
    Abstract: At the time of fabricating a silicon single crystal wafer from a nitrogen-doped silicon single crystal grown according to the Czochralski method, a silicon single crystal wafer covered with a region in which an oxygen precipitation bulk micro defect and an oxidation induced stacking fault mixedly exist is subjected to heat treatment at a temperature of 1100 to 1300° C. in a reducing gas or inert gas atmosphere. In such a manner, a method of fabricating a high-quality silicon single crystal wafer and a silicon single crystal wafer in which no grown-in crystal defects exist in the whole surface and oxygen precipitation bulk micro defects (BMD) are formed at a sufficiently high density to display the IG effect on the inner side can be provided. The single crystal wafer can be suitably used to form an operation region of a semiconductor device.
    Type: Application
    Filed: August 5, 2002
    Publication date: February 13, 2003
    Applicant: TOSHIBA CERAMICS CO., LTD.
    Inventors: Masayuki Watanabe, Junichi Osanai, Akihiko Kobayashi, Kazuhiko Kashima, Hiroyuki Fujimori
  • Patent number: 5744401
    Abstract: A silicon wafer is mirror-polished until obtaining surface roughness Ra of 0.70-1.00 nm, Rq of 0.80-1.10 nm, or Rt of 4.50-7.00 nm. The resulting wafer is heat-treated at a temperature not lower than 1,200.degree. C. for 30 minutes to 4 hours in a hydrogen gas atmosphere. According to another aspect, a silicon wafer is mirror-polished until obtaining surface roughness values Ra' of 0.08-0.70 nm, rms of 0.10-0.90 nm, and P-V of 0.80-5.80 nm in a square area of 90 .mu.m by 90 .mu.m, and surface roughness values Ra' of 0.13-0.40 nm, rms of 0.18-0.50 nm, and P-V of 1.30-2.50 nm in a square area of 500 nm by 500 nm. The resulting wafer is heat-treated at 1,100.degree.-1,300.degree. C. for 30 minutes to 4 hours in a hydrogen gas atmosphere.
    Type: Grant
    Filed: March 22, 1996
    Date of Patent: April 28, 1998
    Assignee: Toshiba Ceramics Co., Ltd.
    Inventors: Hiroshi Shirai, Jun Yoshikawa, Youji Ogawa, Kazuhiko Kashima, Kazuya Ookubo, Yukari Kohtari, Norihiro Shimoi, Masayuki Sanada, Shuji Tobashi
  • Patent number: 4910156
    Abstract: A silicon wafer and a method of producing a silicon wafer comprising a phosphor-doping method of doping phosphor into a single silicon crystals by transmuting isotope Si.sup.30 contained in said single silicon crystals made by the CZ method or the MCZ method into p.sup.31 under neutron irradiation to said single silicon crystals.
    Type: Grant
    Filed: December 22, 1987
    Date of Patent: March 20, 1990
    Assignee: Toshiba Ceramics Co., Ltd.
    Inventors: Shin'ichiro Takasu, Michihiro Ohwa, Kazuhiko Kashima, Eiichi Toji, Kazumoto Homma