Patents by Inventor Kazuhiko Nishi

Kazuhiko Nishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9145337
    Abstract: Provided is a fiber reinforced cement based mixed material having high tensile strength and high toughness, the mixed material comprising a cementitious composition with fast development of early strength; a small hydration heat temperature; and a small shrinkage during curing. The fiber reinforced cement based mixed material contains 100 wt. parts of cement, 5-30 wt. parts of silica fume, 30-80 wt. parts of at least one pozzolanic material excluding the silica fume, 5-25 wt. parts of limestone powder, at least one chemical admixture, water, 70-150 wt. parts of aggregate having a largest aggregate diameter of 1.2-3.5 mm, and fibers, wherein at least some of the fibers comprise a fiber having asperities formed in the surface, the fiber having asperities being formed such that a ratio (h/H) of a depth h of each of recessed portions among the asperities to a smallest cross-sectional diameter H thereof is 0.05-0.8.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: September 29, 2015
    Assignee: TAISEI CORPORATION
    Inventors: Yoshihiro Tanaka, Osamu Hashimoto, Jun Sakamoto, Kazuhiko Nishi
  • Publication number: 20140326168
    Abstract: Provided is a fiber reinforced cement based mixed material having high tensile strength and high toughness, the mixed material comprising a cementitious composition with fast development of early strength; a small hydration heat temperature; and a small shrinkage during curing. The fiber reinforced cement based mixed material contains 100 wt. parts of cement, 5-30 wt. parts of silica fume, 30-80 wt. parts of at least one pozzolanic material excluding the silica fume, 5-25 wt. parts of limestone powder, at least one chemical admixture, water, 70-150 wt. parts of aggregate having a largest aggregate diameter of 1.2-3.5 mm, and fibers, wherein at least some of the fibers comprise a fiber having asperities formed in the surface, the fiber having asperities being formed such that a ratio (h/H) of a depth h of each of recessed portions among the asperities to a smallest cross-sectional diameter H thereof is 0.05-0.8.
    Type: Application
    Filed: November 14, 2012
    Publication date: November 6, 2014
    Applicant: TAISEI CORPORATION
    Inventors: Yoshihiro Tanaka, Osamu Hashimoto, Jun Sakamoto, Kazuhiko Nishi
  • Patent number: 8852337
    Abstract: Provided is a fiber reinforced cement based mixed material capable of securing high tensile strength and high toughness even after development of a crack. A fiber reinforced cement based mixed material contains cement, a mineral admixture, water, a chemical admixture, aggregate particles, and fibers, the aggregate particles contained in the fiber reinforced cement based mixed material in a proportion of 50 to 95% in terms of a weight ratio to the total weight of the cement and the mineral admixture, wherein a mean particle diameter of the aggregate particles is 0.2 to 0.8 mm, and at least some of the fibers is formed to be a bumpy fiber having asperities formed in the surface thereof, and a ratio (h/H) of a depth h of each of recessed portions among the asperities of the bumpy fiber to a smallest cross-sectional diameter H thereof is 0.05 to 0.8.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: October 7, 2014
    Assignee: Taisei Corporation
    Inventors: Yoshihiro Tanaka, Osamu Hashimoto, Kazuhiko Nishi
  • Publication number: 20130324643
    Abstract: Provided is a fiber reinforced cement based mixed material capable of securing high tensile strength and high toughness even after development of a crack. A fiber reinforced cement based mixed material contains cement, a mineral admixture, water, a chemical admixture, aggregate particles, and fibers, the aggregate particles contained in the fiber reinforced cement based mixed material in a proportion of 50 to 95% in terms of a weight ratio to the total weight of the cement and the mineral admixture, wherein a mean particle diameter of the aggregate particles is 0.2 to 0.8 mm, and at least some of the fibers is formed to be a bumpy fiber having asperities formed in the surface thereof, and a ratio (h/H) of a depth h of each of recessed portions among the asperities of the bumpy fiber to a smallest cross-sectional diameter H thereof is 0.05 to 0.8.
    Type: Application
    Filed: February 7, 2012
    Publication date: December 5, 2013
    Inventors: Yoshihiro Tanaka, Osamu Hashimoto, Kazuhiko Nishi
  • Publication number: 20070286887
    Abstract: Fine powders of a slightly soluble amino acid having an average particle size of 0.1 to 5 ?m, may be obtained by wet milling the slightly soluble amino acid. These powders are useful for preparing suspensions in which the fine powder is uniformly and stably dispersed.
    Type: Application
    Filed: June 7, 2007
    Publication date: December 13, 2007
    Applicant: AJINOMOTO CO., INC
    Inventors: Meguru Kaminoyama, Kazuhiko Nishi, Tohru Kouda, Susumu Tsujimoto
  • Patent number: 5921478
    Abstract: A dispersion method for uniformly dispersing solid or liquid fine particles in a solvent utilizes a supercritical fluid. A dispersoid of a solid, a liquid or the like is mixed with a solvent, and the resulting mixture is fed to a supercritical vessel. A supercritical solvent is then fed to the supercritical vessel and heated and compressed to a level higher than the critical temperature and critical pressure thereof to convert it to a supercritical fluid. The supercritical fluid and mixture of dispersoid and solvent are mixed together to form a supercritical mixture, which is released to atmospheric pressure in an explosion-crashing tank and subjected to collision within the explosion-crashing tank to efficiently disperse the dispersoid in the solvent.
    Type: Grant
    Filed: November 20, 1997
    Date of Patent: July 13, 1999
    Assignee: Inoue MFG., Inc.
    Inventors: Mitsuo Kamiwano, Kazuhiko Nishi, Yoshitaka Inoue
  • Patent number: 5416497
    Abstract: A video display control system displays a multicolor animation pattern on a screen of a video display unit. The video display control system is mainly constructed by a video RAM (VRAM) and a video display processor (VDP). The VRAM stores animation pattern data, display position data and at least two color data. The VDP reads these data and makes an animation pattern image displayed in at least two colors at a display position on the screen. The animation pattern image, two colors and display position are determined by the animation pattern data, two color data and display position data. In another video display control system, the VRAM stores at least two sets of animation pattern data, display position data and color data. When displaying two animation patterns, the VDP effects a logical operation on the two color data with respect to the overlapping portion of the two patterns and makes the overlapping portion displayed in a new color corresponding to the operation result.
    Type: Grant
    Filed: September 11, 1992
    Date of Patent: May 16, 1995
    Assignees: ASCII Corporation, Nippon Gakki Seizo Kabushiki Kaisha
    Inventors: Kazuhiko Nishi, Takatoshi Ishii, Ryozo Yamashita, Shigemitsu Yamaoka, Takatoshi Okumura
  • Patent number: 5133002
    Abstract: A radiotelephone system having a base unit and a plurality of subordinate units for carrying out radiocommunication between the base unit and the subordinate units. The base unit sends transmitting carriers to the subordinate units and gets receiving carriers from the subordinate units. The system includes a first frequency varying part for periodically shifting transmitting/receiving carrier frequencies of the base unit from a given frequency of one operating interval to another frequency of another operating interval. A first synchronizing signal part generates a synchronizing signal in synchronism with a time period determined from the shifting of the carrier frequencies. A second synchronizing signal part extracts a synchronizing signal from a receiving carrier signal received by each of the subordinate units.
    Type: Grant
    Filed: July 20, 1990
    Date of Patent: July 21, 1992
    Assignee: ASCII Corporation
    Inventors: Hajime Kikuchi, Kazuhiko Nishi, Youichi Kawaguchi
  • Patent number: 4897636
    Abstract: A video display control system is capable of moving a part of a still image from a first display area to a second display area on a screen. The video display control system includes a memory composed of a plurality of memory locations for storing a plurality of display data representative of images of display elements on the screen. First and second registers retain first and second area data representative of the first and second display areas, and an address data generator generates from these area data first and second address data, the first address data indicating memory locations which store display data corresponding to the first display area, the second address data indicating second memory locations which store display data corresponding to the second display area.
    Type: Grant
    Filed: December 21, 1987
    Date of Patent: January 30, 1990
    Assignees: ASCII Corporation, Nippon Gakki Seizo Kabushiki Kaisha
    Inventors: Kazuhiko Nishi, Takatoshi Ishii, Ryozo Yamashita, Shigemitsu Yamaoka, Takatoshi Okumura, Minoru Morimoto
  • Patent number: 4864289
    Abstract: A video display control system displays a multicolor animation pattern on a screen of a video display unit. The video display control system is mainly constructed by a video RAM (VRAM) and a video display processor (VDP). The VRAM stores animation pattern data, display position data and at least two color data. The VDP reads these data and makes an animation pattern image displayed in at least two colors at a display position on the screen. The animation pattern image, two colors and display position are determined by the animation pattern data, two color data and display position data. In another video display control system, the VRAM stores at least two sets of animation pattern data, display position data and color data. When displaying two animation patterns, the VDP effects a logical operation on the two color data with respect to the overlapping portion of the two patterns and makes the overlapping portion displayed in a new color corresponding to the operation result.
    Type: Grant
    Filed: January 23, 1987
    Date of Patent: September 5, 1989
    Assignees: ASCII Corporation, Nippon Gakki Seizo Kabushiki Kaisha
    Inventors: Kazuhiko Nishi, Takatoshi Ishii, Ryozo Yamashita, Shigemitsu Yamaoka, Takatoshi Okumura
  • Patent number: 4812828
    Abstract: A video display processor (VDP) is connectable to an input control device such as a light pen and a mouse. The VDP comprises a counter circuit which is composed of an X counter and a Y counter. When a mouse mode is selected, X and Y pulse signals are supplied to the X and Y counters so that the contents of the X and Y counters represent the amount of movement of the mouse. When a central processing unit (CPU) connected to the VDP reads the contents of the X and Y counters in this mouse mode, the X and Y counters are reset. When a light pen mode is selected, the X and Y counters effect a count operation of a clock signal generated in the VDP in synchronism with the display of image on a screen so that the contents of the X and Y counters represents X-Y coordinates of a display element which is currently displayed on the screen.
    Type: Grant
    Filed: October 7, 1987
    Date of Patent: March 14, 1989
    Assignees: ASCII Corporation, Nippon Gakki Seizo Kabushiki Kaisha
    Inventors: Kazuhiko Nishi, Takatoshi Ishii, Ryozo Yamashita, Shigemitsu Yamaoka, Takatoshi Okumura
  • Patent number: 4804948
    Abstract: A video display control system displays a video image composed of a plurality of display elements on a screen of a video display unit. The system comprises a memory (VRAM) for storing a plurality of color codes each representing at least one display element and a video display controller (VDP). The VDP comprises a mode register for selecting one of normal display and transparency processing modes, display processing circuit for reading the color codes from the VRAM, a backdrop color register for storing a color code such as one representing a backdrop color, a detection circuit for detecting a predetermined color code from the color codes read by the display processing circuit, and a selector controlled by an output of the detection circuit. In the normal display mode, the selector outputs all color codes read by the display processing circuit to the display unit.
    Type: Grant
    Filed: July 27, 1987
    Date of Patent: February 14, 1989
    Assignees: ASCII Corp., Nippon Gakki Seizo Kabushiki Kaisha
    Inventors: Kazuhiko Nishi, Takatoshi Ishii, Ryozo Yamashita, Shigemitsu Yamaoka, Takatoshi Okumura
  • Patent number: 4747042
    Abstract: An improved display control system for use in a computer is disclosed which is equipped with functions of X, Y addressing and area movement so as to reduce the execution time necessary for display operations of the computer. Also, in this display control system, means for executing line commands is composed of the hardware so as to reduce the execution time necessary for display operations on the line commands.
    Type: Grant
    Filed: December 19, 1984
    Date of Patent: May 24, 1988
    Assignee: Ascii Corporation
    Inventors: Takatoshi Ishii, Ryozo Yamashita, Kazuhiko Nishi
  • Patent number: 4737772
    Abstract: A video display processor (VDP) produces a video signal by which a black and white image of an increased gradation can be displayed on a video display unit. The VDP reads from a video RAM (VRAM) either color codes each representative of a color of each display element, or amplitude data representative of amplitudes of a video signal to be reproduced. When displaying an image based on the color codes, the color codes are converted by a color palette circuit into color data each composed of three primary color data, and then supplied to a digital color encoder. The digital color encoder multiplies each of the three color data by predetermined coefficients at proper phase timings to output data representative of three chrominance signals. This output data is summed by an adder circuit and then converted into an analog signal to be supplied to the video display unit as the video signal. When displaying an image based on the amplitude data, the color palette circuit converts the amplitude data into gradation data.
    Type: Grant
    Filed: May 29, 1985
    Date of Patent: April 12, 1988
    Assignees: Ascii Corporation, Nippon Gakki Seizo Kabushiki Kaisha
    Inventors: Kazuhiko Nishi, Takatoshi Ishii, Ryozo Yamashita, Shigemitsu Yamaoka, Takatoshi Okumura
  • Patent number: 4737778
    Abstract: There is provided a video display controller which can vertically and horizontally shift a whole video image displayed on a screen of a video display unit. The video display controller comprises an image data read circuit which reads the image data from a video RAM, a register into which data representative of amount of shift of the video image is stored by a central processing unit, and a first counter which cyclicly counts a clock signal. An adder adds the data contained in the register and a count output of the first counter, and at a timing determined by this addition result a predetermined value is preset into a second counter. This second counter counts the clock signal from the predetermined value, and the image data read by the image data read circuit is outputted to the video display unit at a timing in accordance with a count output of this second counter. The register, first counter, adder and second counter are provided in each of vertical and horizontal scanning control circuits.
    Type: Grant
    Filed: May 22, 1985
    Date of Patent: April 12, 1988
    Assignees: Ascii Corporation, Nippon Gakki Seizo Kabushiki Kaisha
    Inventors: Kazuhiko Nishi, Takatoshi Ishii, Ryozo Yamashita, Shigemitsu Yamaoka, Takatoshi Okumura
  • Patent number: 4731742
    Abstract: A video display control system for displaying a video image on a screen of a video display unit. This video display control system basically comprises a VRAM (video RAM) and a video display processor (VDP). The VRAM has memory locations corresponding to display elements on the screen. The VDP includes a first register for receiving area information identifying a display area on the screen, an address generator for generating addresses of memory locations corresponding to the display area in accordance with the area information, and a memory accessing circuit for accessing the memory locations having the addresses. Therefore, the memory accessing operation through this VDP does not need a complicated support by a central processing unit. The VDP further comprises a second register for storing a color code supplied from an external device or read from the VRAM.
    Type: Grant
    Filed: March 15, 1985
    Date of Patent: March 15, 1988
    Assignees: Ascii Corporation, Nippon Gakki Seizo Kabushiki Kaisha
    Inventors: Kazuhiko Nishi, Takatoshi Ishii, Ryozo Yamashita, Shigemitsu Yamaoka, Takatoshi Okumura, Minoru Morimoto
  • Patent number: 4706470
    Abstract: A system and apparatus for controlling the operation of a vibrating compressor using a predetermined frequency corresponding to the load thereof, comprising a first sensor for detecting a temperature of pressure corresponding to the saturated vapor pressure of a refrigerant sucked by a vibrating compressor, a second sensor for detecting a temperature or pressure corresponding to the saturated vapor pressure of the refrigerant compressed and discharged by the compressor, and a control section for generating a drive power of a predetermined frequency based on the temperatures and pressures detected by the first and second sensors, and characterized in that the compressor is driven by a drive power generated by the control section.
    Type: Grant
    Filed: May 14, 1986
    Date of Patent: November 17, 1987
    Assignee: Sawafuji Electric Co., Ltd.
    Inventors: Naoki Akazawa, Kazuhiko Nishi, Naoya Kawakami, Yoshiaki Fujisawa, Noriyoshi Yamada
  • Patent number: 4684942
    Abstract: A video display controller is provided with a color palette circuit which is capable of converting, at a high conversion rate, color codes read from a VRAM (video RAM) into RGB color data to be supplied to a CRT display unit. The color palette circuit comprises a plurality of color data registers each storing one RGB color data and is supplied with a timing signal synchronized with the display timing of display elements on the CRT display screen. Each color code data including at least two color codes and read from an address of the VRAM is first supplied to a selection circuit which includes at least two decoders. Each decoder decodes the corresponding color codes to generate a selection signal which enables one of the color data registers to output the RGB color data contained therein.
    Type: Grant
    Filed: May 22, 1985
    Date of Patent: August 4, 1987
    Assignees: Ascii Corporation, Nippon Gakki Seizo Kabushiki Kaisha
    Inventors: Kazuhiko Nishi, Takatoshi Ishii, Ryozo Yamashita, Shigemitsu Yamaoka, Takatoshi Okumura
  • Patent number: 4660070
    Abstract: A video display processor (VDP) for use with a central processing unit, a video RAM (VRAM) and a video display unit is capable of writing video image data supplied from an external video device such as a television set into the VRAM. The VDP comprises a first input terminal for receiving the external video image data and a second input terminal for receiving horizontal and vertical synchronization signals from the external video device. The VDP generates address data in accordance with the horizontal and vertical synchronization signals and supplies the address data to the VRAM when processing of the external video image data is designated. The VDP also supplies the received external video image data to the VRAM thereby to write the external video image data into addresses of the VRAM designated by the address data.
    Type: Grant
    Filed: May 22, 1985
    Date of Patent: April 21, 1987
    Assignees: ASCII Corporation, Nippon Gakki Seizo Kabushiki Kaisha
    Inventors: Kazuhiko Nishi, Takatoshi Ishii, Ryozo Yamashita, Shigemitsu Yamaoka, Takatoshi Okumura
  • Patent number: 4635048
    Abstract: A video display controller which can display foregrounds as well as backgrounds of display patterns on a screen of a video display unit in a plurality of colors. The video display controller comprises a plurality of color information registers, in each of which a pair of color code data representative of foreground and background colors of one display pattern are stored. A memory is provided for storing a plurality of pattern data, a plurality of pattern name data each designating one of the display patterns to be displayed on a respective one of display portions of the screen, and a plurality of color selection data each corresponding to a respective one of the display portions. A sequence controller sequentially reads the pattern data designated by the pattern name data and the color selection data in accordance with synchronization signals.
    Type: Grant
    Filed: February 6, 1985
    Date of Patent: January 6, 1987
    Assignees: Ascii Corporation, Nippon Gakki Seizo Kabushiki Kaisha
    Inventors: Kazuhiko Nishi, Takatoshi Ishii, Ryozo Yamashita, Shigemitsu Yamaoka, Takatoshi Okumura