Patents by Inventor Kazuhiko Sagara

Kazuhiko Sagara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4956688
    Abstract: A bipolar memory of a construction having high immunity from soft error attributable to alpha rays is provided. The transistors of a flip flop, i.e., the essential circuit of the memory cell, are inverted, and the load device thereof has a shielding arrangement for shielding the flip flop from the noise produced within the substrate. Either pnp type transistors or Schottky barrier diodes are employed as the load devices. A buried layer (ordinarily, an n type layer) and a doped layer of the reverse conductivity type (ordinarily the p type) are formed in the region where the device is provided. A reverse bias is applied across the buried layer and the doped layer to shut off the noise produced within the substrate.
    Type: Grant
    Filed: June 27, 1989
    Date of Patent: September 11, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Noriyuki Honma, Tohru Nakamura, Kazuo Nakazato, Motoaki Matsumoto, Tetsuya Hayashida, Masaharu Kubo, Kazuhiko Sagara
  • Patent number: 4948599
    Abstract: Disclosed herein is a process for the continuous and quick production of cheese curds from milk, which comprises cooling a concentrated milk which has been obtained by ultrafiltration, adjusting its pH to 4.8-5.8 without coagulation, adding a milk-coagulating enzyme and/or a lactic acid bacterium starter, and the quickly heating the resultant mixture to 25.degree.-84.degree. C., whereby cheese curds are continuously formed, the heating of the mixture preferably being effected by heating a permeate separated out by the ultrafiltration and then mixing the heated permeate with the mixture. The thus-obtained cheese curds affording cheese having smooth texture.
    Type: Grant
    Filed: April 13, 1989
    Date of Patent: August 14, 1990
    Assignee: Snow Brand Milk Products Co., Ltd.
    Inventors: Kazuhiko Sagara, Kunio Ueda, Toshikazu Shimada, Toshiaki Ishii
  • Patent number: 4905078
    Abstract: A semiconductor device includes a semiconductor layer provided above a pair of bipolar transistors formed in a surface region of a semiconductor body. Schottky barrier diodes and resistors are formed in the semiconductor layer. The pair of bipolar transistors, the Schottky barrier diodes and the resistors are electrically connected to constitute a bipolar memory. Since the Schottky barrier diodes and the resistors can be formed above the bipolar transistors, an area required for the memory cell can be made greatly small and the occurrence of an hindrance caused by .alpha. particles is minimal.
    Type: Grant
    Filed: August 11, 1987
    Date of Patent: February 27, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhiko Sagara, Yoichi Tamaki, Noriyuki Homma, Tohru Nakamura
  • Patent number: 4858184
    Abstract: A bipolar memory of a construction having high immunity to soft error attributable to alpha rays is provided. The transistors of a flip flop, i.e., the essential circuitry of the memory cell, are inverted and the load device thereof has shielding means for shielding the flip flop from the noise produced within the substrate. Bipolar transistors and Schottky barrier diodes are employed as the load devices. A buried layer (ordinarily, an n type layer) and a doped layer of the reverse conductivity type (ordinarily the p type) are formed in a region where the device is provided, and a reverse bias is applied across the buried layer and the doped layer to shut off the noise produced within the substrate.
    Type: Grant
    Filed: April 27, 1987
    Date of Patent: August 15, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Noriyuki Homma, Tohru Nakamura, Kazuo Nakazato, Motoaki Matsumoto, Tetsuya Hayashida, Masaharu Kubo, Kazuhiko Sagara
  • Patent number: 4829361
    Abstract: A semiconductor device wherein a layer doped with impurities is provided between a buried layer and an epitaxial layer, said layer doped with impurities having a conductivity of the type opposite to that of said buried layer and said epitaxial layer, a reversely biasing voltage is applied across the buried layer and the layer doped with impurities, and side surfaces of the epitaxial layer are surrounded by an insulator.This helps effectively prevent the element formed in the epitaxial layer from being affected by .alpha.-particles and greatly improve reliability of the semiconductor device.
    Type: Grant
    Filed: November 16, 1987
    Date of Patent: May 9, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhiko Sagara, Tohru Nakamura, Kazuo Nakazato, Tokuo Kure, Kiyoji Ikeda, Noriyuki Homma
  • Patent number: 4819054
    Abstract: A bipolar type of semiconductor integrated circuit device is provided with U-shaped grooves which are formed by cutting a main surface of a semiconductor body to form isolation regions between bipolar transistors. A silicon oxide film can be formed in the U-shaped grooves by thermal oxidation simultaneously with the formation of a silicon oxide film used to form isolation regions between each collector contact region and base region. No separate step is needed for forming the silicon oxide film between the collector contact region and the base region. The thickness of the silicon oxide film can be controlled, and has a sufficient thickness even at its two edges, i.e., at its boundaries with the U-shaped grooves, so that the bipolar transistors exhibit good electrical characteristics. Namely, the collector resistance thereof does not increase, and the breakdown voltage at the pn junction between the collector region and the base region does not decrease.
    Type: Grant
    Filed: February 6, 1987
    Date of Patent: April 4, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Mikinori Kawaji, Toshihiko Takakura, Akihisa Uchida, Shigeo Kuroda, Yoichi Tamaki, Takeo Shiba, Kazuhiko Sagara, Masao Kawamura
  • Patent number: 4812894
    Abstract: A semiconductor device includes a first insulation film formed on a monocrystalline substrate and having an opening, a monocrystalline semiconductor layer formed so as to protrude into the first insulation film, and a conductive layer formed in contact with the side section of the monocrystalline semiconductor layer and extending over a second insulation film formed on the monocrystalline semiconductor layer.
    Type: Grant
    Filed: May 3, 1988
    Date of Patent: March 14, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Tohru Nakamura, Kazuo Nakazato, Noriyuki Homma, Kazuhiko Sagara, Takeo Shiba, Tokuo Kure, Tetsuya Hayashida
  • Patent number: 4729965
    Abstract: This invention relates to a method of producing a semiconductor device which is suitable for forming a bipolar transistor having less fluctuation of characteristics at a high production yield.In accordance with the present invention, a graft base (or an extrinsic base) 20 is formed by doping an impurity from a polycrystalline silicon film 13, while an emitter is formed by lithographic technique.Since the emitter is formed by lithographic technique, the position at which the emitter is to be formed unavoidably changes at the time of mask alignment, but its influence upon transistor characteristics is negligible. Therefore, bipolar transistors having far more uniform characteristics can be formed far more easily than with the method which forms the emitter by self-alignment.
    Type: Grant
    Filed: April 9, 1986
    Date of Patent: March 8, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Yoichi Tamaki, Kazuhiko Sagara, Norio Hasegawa, Shinji Okazaki, Toshihiko Takakura, Hirotaka Nishizawa