Abstract: A transfer processing device includes an arithmetic instruction number acquisition circuit, a buffer circuit, a transfer information acquisition circuit, and a software processing unit. The arithmetic instruction number acquisition circuit acquires a transfer instruction number corresponding to transfer information which is information related to the next transfer destination of an arithmetic instruction. The buffer circuit is arranged between the arithmetic instruction number acquisition circuit and the transfer information acquisition circuit, and temporarily stores and relays the arithmetic instruction and the arithmetic instruction number supplied from the arithmetic instruction number acquisition circuit to the transfer information acquisition circuit. The transfer information acquisition circuit acquires transfer information on the basis of the arithmetic instruction number, and gives the acquired transfer information to the arithmetic instruction.

Abstract: Each NIC performs an aggregation calculation of data output from each processor in a normal order including a head NIC located at a head position of a first pipeline connection, an intermediate NIC located at an intermediate position, and a tail NIC located at a tail position, and when the aggregation calculation in the tail NIC is completed, each NIC starts distribution of an obtained aggregation result, distributes the aggregation result in a reverse order including the tail NIC, the intermediate NIC, and the head NIC, and outputs the aggregation result to the processor of the communication interface.

Abstract: A distributed processing node includes a computing device that calculates gradient data of a loss function from an output result obtained by inputting learning data to a learning target model, an interconnect device that aggregates gradient data between the distributed processing node and other distributed processing nodes, a computing function unit that is provided in a bus device and performs processing of gradient data from the computing device, and a DMA controller that controls DMA transfer of gradient data between the computing device and the bus device and DMA transfer of gradient data between the bus device and the interconnect device.

Abstract: A distributed deep learning system includes nodes (1-n, n=1, . . . , 4) and a network. The node (1-n) includes GPUs (11-n-1 and 11-n-2), and an FPGA (12-n). The FPGA (12-n) includes a plurality of GPU reception buffers, a plurality of network transmission buffers that store data transferred from the GPU reception buffers, a plurality of network reception buffers that store aggregated data received from other nodes, and a plurality of GPU transmission buffers that store data transferred from the network reception buffers. The GPUs (11-n-1 and 11-n-2) DMA-transfer data to the FPGA (12-n). The data stored in the GPU transmission buffers is DMA-transferred to the GPUs (11-n-1 and 11-n-2).

Abstract: A distributed processing system including a plurality of distributed systems, transmission media connecting the plurality of distributed systems and a control node connected to the plurality of distributed systems, wherein each of the distributed systems includes one or more distributed nodes constituting a distributed node group and a piece of electric equipment accommodating the distributed node group. Each of the distributed nodes includes interconnects to connect to any of the transmission media and/or other distributed nodes; and the control node determines, based on a quantity of computational resources required for a job, distributed systems, distributed systems and distributed nodes in the distributed systems to execute the job from the plurality of distributed systems, selects a connection path for data to be processed among the distributed systems, and provides information about an interconnect connection path for the distributed nodes to execute the job.

Abstract: A distributed processing system to which a plurality of distributed nodes are connected, each of the distributed nodes including a plurality of arithmetic devices and an interconnect device, wherein, in the interconnect device and/or the arithmetic devices of one of the distributed nodes, memory areas are assigned to each job to be processed by the distributed processing system, and direct memory access between memories for processing the job is executed at least between interconnect devices, between arithmetic devices or between an interconnect device and an arithmetic device.

Abstract: A distributed deep learning system includes a plurality of computation nodes mutually connected through a communication network, wherein each of the plurality of computation nodes includes a network processing unit including: a reception section that receives an OAM packet indicating states of the plurality of computation nodes; an OAM processing section that makes a record, in the OAM packet received by the reception section, of whether or not a partial arithmetic operation result is outputted from an arithmetic operation unit of the own node; and a transmission section that transmits the OAM packet including the record made by the OAM processing section to another computation node, wherein the OAM processing section, depending on the state of the other computation node indicated by the OAM packet, causes the transmission section to transmit the partial arithmetic operation result stored in a storage unit to the other computation node.

Abstract: A distributed deep learning system includes a plurality of calculation nodes connected to one another via a communication network. Each of the plurality of calculation nodes includes a computation unit that calculates a matrix product included in computation processing of a neural network and outputs a partial computation result, a storage unit that stores the partial computation result, and a network processing unit including a transmission unit that transmits the partial computation result to another calculation node, a reception unit that receives a partial computation result from another calculation node, an addition unit that obtains a total computation result, which is a sum of the partial computation result stored in the storage unit and the partial computation result from another calculation node, a transmission unit that transmits the total computation result to another calculation node, and a reception unit that receives a total computation result from another calculation node.

Abstract: An embodiment is a computer including a plurality of accelerators, a computer for distributed processing includes a plurality of accelerators to each of which a part of a neural network is assigned and each of which is configured to derive a learning result based on input data and update each parameter value included in the part of the neural network by using the learning result; a plurality of network interface circuits each of which is configured to transmit and receive information on learning including the learning result via a network, and an arithmetic processing unit that is configured to control the plurality of accelerators and the plurality of network interface circuits to cause each of the plurality of accelerators to derive a learning result based on input data and to cause the plurality of network interface circuits to transmit and receive information on learning including the learning result.

Abstract: An OLT (10) is provided with a priority control bypass circuit (16) and an encryption/decryption bypass circuit (17), or an ONU (20) is provided with a priority control bypass circuit (26) and an encryption/decryption bypass circuit (27), and one or both of encryption/decryption processing and priority control processing are bypassed in accordance with a priority control bypass instruction (BP) and an encryption/decryption bypass instruction (BE), which are set in advance. This reduces a processing delay that occurs in the OLT or the ONU.

Abstract: An OLT (10) is provided with a priority control bypass circuit (16) and an encryption/decryption bypass circuit (17), or an ONU (20) is provided with a priority control bypass circuit (26) and an encryption/decryption bypass circuit (27), and one or both of encryption/decryption processing and priority control processing are bypassed in accordance with a priority control bypass instruction (BP) and an encryption/decryption bypass instruction (BE), which are set in advance. This reduces a processing delay that occurs in the OLT or the ONU.

Abstract: The invention aims to execute image processing in synchronization with predetermined procedures with a single controller and eliminate an image pickup inhibit period for preventing incomplete image pickup. Pickup completing conditions of a plurality of types that are established when the image data is obtained from a predetermined image pickup unit (one of a camera 30a to a camera 30c) are stored, and processing contents of the image pickup unit includes identifying whether or not the image data is obtained from the predetermined image pickup unit, determining whether or not any of the pickup completing conditions of the plurality of types is established, and executing an assignment process to the image data used for the execution of the measurement unit associated with the pickup completing condition that is determined to be established.

Abstract: In a transmission node, a portion of the control information is separated into M (M is an integer) parts of control information blocks having N (N is an integer) bit length. A control information parity having (8?N) bit length is added to control information block i. The control information block is encoded to M parts of control information having 8 bit length according to a predetermined control information bit array. The control information parity and the control information bit array are set such that Hamming distance of each of the control information code is d, and Hamming distance of the control information 10B code is D (d and D are integers). In a receiving node, the control information code is separated into the control information block and the control information parity. Parity check is performed. When an error is detected, error processing is performed.

Abstract: In a transmission node, a portion of the control information is separated into M (M is an integer) parts of control information blocks having N (N is an integer) bit length. A control information parity having (8-N) bit length is added to control information block i. The control information block is encoded to M parts of control information having 8 bit length according to a predetermined control information bit array. The control information parity and the control information bit array are set such that Hamming distance of each of the control information code is d, and Hamming distance of the control information 10B code is D (d and D are integers). In a receiving node, the control information code is separated into the control information block and the control information parity. Parity check is performed. When an error is detected, error processing is performed.