Patents by Inventor Kazuhiko Yamamoto

Kazuhiko Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230395047
    Abstract: An audio analysis method that is realized by a computer system includes setting a maximum tempo curve representing a temporal change of a maximum tempo value and a minimum tempo curve representing a temporal change of a minimum tempo value in accordance with an instruction from a user, and analyzing an audio signal representing a performance sound of a musical piece, thereby estimating a tempo of the musical piece within a restricted range between a maximum value represented by the maximum tempo curve and a minimum value represented by the minimum tempo curve.
    Type: Application
    Filed: August 21, 2023
    Publication date: December 7, 2023
    Inventor: Kazuhiko YAMAMOTO
  • Publication number: 20230395052
    Abstract: An audio analysis method that is realized by a computer system includes estimating a plurality of beat points of a musical piece by analyzing an audio signal representing a performance sound of the musical piece, receiving an instruction from a user to change a location of at least one beat point of the plurality of beat points, and updating a plurality of locations of the plurality of beat points in response to the instruction from the user.
    Type: Application
    Filed: August 21, 2023
    Publication date: December 7, 2023
    Inventor: Kazuhiko YAMAMOTO
  • Patent number: 11683943
    Abstract: A memory device including a first conductive layer; a second conductive layer; a resistance change region provided between the first conductive layer and the second conductive layer; a first region provided between the resistance change region and the first conductive layer, the first region including a first element selected from the group consisting of niobium, vanadium, tantalum, and titanium, and a second element selected from the group consisting of oxygen, sulfur, selenium, and tellurium, the first region having a first atomic ratio of the first element to the second element; and a second region provided between the first region and the resistance change region, the second region including the first element and the second element, the second region having a second atomic ratio of the first element to the second element, the second atomic ratio being smaller than the first atomic ratio.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: June 20, 2023
    Assignee: Kioxia Corporation
    Inventors: Tsunehiro Ino, Yukihiro Nomura, Kazuhiko Yamamoto, Koji Usuda
  • Patent number: 11531098
    Abstract: A radar image processing device performs determination of a pixel including a ghost image and changes the value of the pixel which is determined to include the ghost image on a radar image the focus of which has been changed.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: December 20, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Noboru Oishi, Kazuhiko Yamamoto
  • Patent number: 11514970
    Abstract: A memory device according to an embodiment includes first and second interconnects, memory cells, and a control circuit. In a first process, the control circuit applies a write voltage of a first direction to a memory cell coupled to selected first and second interconnects, and applies a write voltage of a second direction to a memory cell coupled to the selected first interconnect and a non-selected second interconnect. In second processes of first to m-th trial processes, the control circuit applies the write voltage of the second direction to the memory cell coupled to the selected first and second interconnects, and omits a write operation in which the memory cell coupled to the selected first interconnect and the non-selected second interconnect is targeted.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: November 29, 2022
    Assignee: Kioxia Corporation
    Inventors: Marina Yamaguchi, Kensuke Ota, Kazuhiko Yamamoto, Masumi Saitoh
  • Patent number: 11514876
    Abstract: Disclosed is a learning model generation method executed by a computer, including: striking a percussion instrument with a striking member to emit a musical sound; and conducting machine learning upon receiving an input of the musical sound emitted from the percussion instrument, and generating, based on the machine learning, a learning model for outputting numerical values for setting musical performance parameters for an automatic musical performance of the percussion instrument that is struck when the striking member is driven.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: November 29, 2022
    Assignee: YAMAHA CORPORATION
    Inventor: Kazuhiko Yamamoto
  • Patent number: 11508174
    Abstract: An image processing method implemented by a computer includes extracting feature points from captured images that are sequentially generated by an image capture device and include at least a first captured image and a second captured image generated prior to the first captured image, determining whether the number of feature points extracted from the first captured image exceeds a threshold value, and specifying a location of the first captured image relative to the second captured image upon determining that the number of the feature points extracted from the first captured image is below the threshold value.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: November 22, 2022
    Assignee: YAMAHA CORPORATION
    Inventor: Kazuhiko Yamamoto
  • Publication number: 20220262422
    Abstract: A memory device according to an embodiment includes first and second interconnects, memory cells, and a control circuit. In a first process, the control circuit applies a write voltage of a first direction to a memory cell coupled to selected first and second interconnects, and applies a write voltage of a second direction to a memory cell coupled to the selected first interconnect and a non-selected second interconnect. In second processes of first to m-th trial processes, the control circuit applies the write voltage of the second direction to the memory cell coupled to the selected first and second interconnects, and omits a write operation in which the memory cell coupled to the selected first interconnect and the non-selected second interconnect is targeted.
    Type: Application
    Filed: September 9, 2021
    Publication date: August 18, 2022
    Applicant: Kioxia Corporation
    Inventors: Marina YAMAGUCHI, Kensuke OTA, Kazuhiko YAMAMOTO, Masumi SAITOH
  • Patent number: 11398100
    Abstract: Disclosed is an image analysis method implemented by a computer, the method including analyzing a partial image which is a part of an image of a planar subject, generating partial-image analysis data representing a characteristic of the partial image, comparing, for each of a plurality of images, candidate-image analysis data with the partial-image analysis data, the candidate-image analysis data representing a characteristic of each of the plurality of images, and selecting a candidate image among the plurality of images, the candidate image including a part corresponding to the partial image.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: July 26, 2022
    Assignee: YAMAHA CORPORATION
    Inventor: Kazuhiko Yamamoto
  • Publication number: 20210376236
    Abstract: According to one embodiment, a memory device includes a first electrode, a second electrode, and a resistive layer provided between the first electrode and the second electrode, containing at least one of antimony (Sb) and bismuth (Bi) as a first element, and tellurium (Te) as a second element, and having a variable resistance value. The resistive layer includes a first layer having a hexagonal crystal structure containing the first element and the second element. The first layer contains a group 14 element as a third element.
    Type: Application
    Filed: March 15, 2021
    Publication date: December 2, 2021
    Applicant: Kioxia Corporation
    Inventors: Bairu YAN, Yoshiki KAMATA, Kazuhiko YAMAMOTO
  • Patent number: 11187673
    Abstract: The present disclosure relates to an apparatus the for verification, calibration, and/or adjustment of a measuring instrument. The apparatus includes the measuring instrument, a reference measuring instrument, and a smart device. The apparatus performs a measuring operation in which the measuring instrument determines a value of a variable of the medium and the reference instrument determines a reference value of the variable from a sample of the medium. The measuring instrument communicates wirelessly and performs the verification, calibration, and/or adjustment on the basis of the measured value and the associated reference value. The reference measuring instrument is portable and communicates wirelessly with the smart device and the measuring instrument. An application executed on the smart device controls a data transfer between the measuring instrument, the reference measuring device, and/or the device that is required for executing the verification, calibration, and/or adjustment.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: November 30, 2021
    Assignee: Endress+Hauser Conducta GmbH+Co. KG
    Inventors: Tuncay Gülfirat, Kazuhiko Yamamoto, Martin Freudenberger, Bo Ottersten, Martin Lohmann, Oliver Durm
  • Patent number: 11171156
    Abstract: According to an embodiment, a memory device includes a first conductive layer extending in a first direction, a second conductive layer extending in the first direction, a third conductive layer extending in a second direction intersecting with the first direction, an insulating layer provided between the first conductive layer and the second conductive layer, and a dielectric layer provided between the first conductive layer and the third conductive layer, and between the insulating layer and the third conductive layer, the dielectric layer having a first thickness thinner than a second thickness, the first thickness being a thickness between the first conductive layer and the third conductive layer, the second thickness being a thickness between the insulating layer and the third conductive layer, and the dielectric layer including an oxide including at least one of hafnium oxide and zirconium oxide.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: November 9, 2021
    Assignee: Kioxia Corporation
    Inventors: Tsunehiro Ino, Kazuhiko Yamamoto
  • Publication number: 20210296400
    Abstract: A memory device of an embodiment includes: a first conductive layer; a second conductive layer; a resistance change region provided between the first conductive layer and the second conductive layer; a first region provided between the resistance change region and the first conductive layer, the first region including a first element selected from the group consisting of niobium, vanadium, tantalum, and titanium, and a second element selected from the group consisting of oxygen, sulfur, selenium, and tellurium, the first region having a first atomic ratio of the first element to the second element; and a second region provided between the first region and the resistance change region, the second region including the first element and the second element, the second region having a second atomic ratio of the first element to the second element, the second atomic ratio being smaller than the first atomic ratio.
    Type: Application
    Filed: December 17, 2020
    Publication date: September 23, 2021
    Applicant: Kioxia Corporation
    Inventors: Tsunehiro INO, Yukihiro NOMURA, Kazuhiko YAMAMOTO, Koji USUDA
  • Patent number: 11081526
    Abstract: According to one embodiment, a nonvolatile memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction, a third wiring extending in the second direction and spaced from the second wiring in the first direction. An insulating layer includes a first portion between the second wiring and the third wiring, and a second portion protruding from the first portion in a third direction. A chalcogenide layer is between the first wiring and the second wiring, the first wiring and the third wiring, and also the first wiring and the insulating layer. The chalcogenide layer includes a first layer portion, a second layer portion, and a third layer portion. A concentration of a first element in the third layer portion is higher than that in the first and second layer portions.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: August 3, 2021
    Assignee: KIOXIA CORPORATION
    Inventor: Kazuhiko Yamamoto
  • Publication number: 20210091095
    Abstract: According to an embodiment, a memory device includes a first conductive layer extending in a first direction, a second conductive layer extending in the first direction, a third conductive layer extending in a second direction intersecting with the first direction, an insulating layer provided between the first conductive layer and the second conductive layer, and a dielectric layer provided between the first conductive layer and the third conductive layer, and between the insulating layer and the third conductive layer, the dielectric layer having a first thickness thinner than a second thickness, the first thickness being a thickness between the first conductive layer and the third conductive layer, the second thickness being a thickness between the insulating layer and the third conductive layer, and the dielectric layer including an oxide including at least one of hafnium oxide and zirconium oxide.
    Type: Application
    Filed: March 2, 2020
    Publication date: March 25, 2021
    Applicant: Kioxia Corporation
    Inventors: Tsunehiro INO, Kazuhiko YAMAMOTO
  • Publication number: 20210083003
    Abstract: According to one embodiment, a nonvolatile memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction, a third wiring extending in the second direction and spaced from the second wiring in the first direction. An insulating layer includes a first portion between the second wiring and the third wiring, and a second portion protruding from the first portion in a third direction. A chalcogenide layer is between the first wiring and the second wiring, the first wiring and the third wiring, and also the first wiring and the insulating layer. The chalcogenide layer includes a first layer portion, a second layer portion, and a third layer portion. A concentration of a first element in the third layer portion is higher than that in the first and second layer portions.
    Type: Application
    Filed: February 27, 2020
    Publication date: March 18, 2021
    Inventor: Kazuhiko YAMAMOTO
  • Publication number: 20210056303
    Abstract: An image processing method implemented by a computer includes extracting feature points from captured images that are sequentially generated by an image capture device and include at least a first captured image and a second captured image generated prior to the first captured image, determining whether the number of feature points extracted from the first captured image exceeds a threshold value, and specifying a location of the first captured image relative to the second captured image upon determining that the number of the feature points extracted from the first captured image is below the threshold value.
    Type: Application
    Filed: November 10, 2020
    Publication date: February 25, 2021
    Inventor: Kazuhiko YAMAMOTO
  • Publication number: 20200400813
    Abstract: A radar image processing device performs determination of a pixel including a ghost image and changes the value of the pixel which is determined to include the ghost image on a radar image the focus of which has been changed.
    Type: Application
    Filed: September 9, 2020
    Publication date: December 24, 2020
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Noboru OISHI, Kazuhiko YAMAMOTO
  • Patent number: 10840445
    Abstract: A memory device includes a crystal-including layer including a first metal, and a germanium-and-oxygen including layer contacting the crystal-including layer. At least a portion of the crystal-including layer is crystallized. The germanium-and-oxygen including layer includes germanium and oxygen.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: November 17, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuhiko Yamamoto, Kunifumi Suzuki, Tomotaka Ariga
  • Patent number: 10825866
    Abstract: A memory device is described. A first conductive layer extends in a first direction. A second conductive layer extends in the first direction. A third conductive layer extends in a second direction intersecting the first direction. A first oxide region is disposed between the first conductive layer and the third conductive layer and between the second conductive layer and the third conductive layer. A semiconductor region is disposed between the first conductive layer and the first oxide region and between the first conductive layer and the second conductive layer. A second distance between the semiconductor region, which is disposed between the first conductive layer and the second conductive layer, and the third conductive layer, is longer than a first distance between the semiconductor region, which is disposed between the first conductive layer and the first oxide region, and the third conductive layer.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: November 3, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kunifumi Suzuki, Kazuhiko Yamamoto