Abstract: A failure analysis apparatus 10 is composed of an inspection information acquirer 11 for acquiring a failure observed image P2 of a semiconductor device, a layout information acquirer 12 for acquiring layout information, and a failure analyzer 13 for analyzing a failure of the semiconductor device. The failure analyzer 13 has an analysis region setter for comparing an intensity distribution in the failure observed image with a predetermined intensity threshold to extract a reaction region arising from a failure, and for setting an analysis region used in the failure analysis of the semiconductor device, in correspondence to the reaction region. This substantializes a semiconductor failure analysis apparatus, failure analysis method, and failure analysis program capable of securely and efficiently performing the analysis of the failure of the semiconductor device using the failure observed image.

Abstract: A failure analysis apparatus 10 is composed of an inspection information acquirer 11 for acquiring a failure observed image P2 of a semiconductor device, a layout information acquirer 12 for acquiring layout information, and a failure analyzer 13 for analyzing a failure. The failure analyzer 13 extracts as a candidate interconnection for a failure, an interconnection passing an analysis region, out of a plurality of interconnections, using interconnection information to describe a configuration of interconnections in the semiconductor device by a pattern data group of interconnection patterns in respective layers, and, for extracting the candidate interconnection, it performs an equipotential trace of the interconnection patterns using the pattern data group, thereby extracting the candidate interconnection.

Abstract: A failure analysis apparatus 10 is composed of an inspection information acquirer 11 for acquiring a failure observed image P2 of a semiconductor device, a layout information acquirer 12 for acquiring layout information, and a failure analyzer 13 for analyzing a failure. The failure analyzer 13 extracts candidate nets passing at least one of analysis regions set from the failure observed image, out of a plurality of nets in the semiconductor device, and passage counts of the respective candidate nets through the analysis regions, selects a candidate net with the largest passage count as a first failure net, and selects a second failure net with attention to analysis regions where the first failure net does not pass. This substantializes a semiconductor failure analysis apparatus, failure analysis method, and failure analysis program capable of securely and efficiently performing the analysis of the failure of the semiconductor device using the failure observed image.

Abstract: A failure analysis apparatus 10 is composed of an inspection information acquirer 11 for acquiring a failure observed image P2 of a semiconductor device, a layout information acquirer 12 for acquiring layout information, a failure analyzer 13 for analyzing a failure of the semiconductor device, and an analysis screen display controller 14 for letting a display device 40 display information about a result of the analysis. The failure analyzer 13 sets an analysis region with reference to the failure observed image P2, and extracts a net passing the analysis region, from a plurality of nets included in a layout of the semiconductor device. This substantializes a semiconductor failure analysis apparatus, analysis method, and analysis program capable of securely and efficiently performing the analysis of the failure of the semiconductor device.

Abstract: A failure analysis apparatus 10 is composed of an inspection information acquirer 11 for acquiring at least a pattern image P1 of a semiconductor device, a layout information acquirer 12 for acquiring a layout image P3, a failure analyzer 13 for analyzing a failure of the semiconductor device, and an analysis screen display controller 14 for letting a display device 40 display information about the failure analysis. The analysis screen display controller 14 generates a superimposed image in which the pattern image P1 and the layout image P3 are superimposed, as an image of the semiconductor device to be displayed by the display device 40, and sets a transmittance of the layout image P3 relative to the pattern image P1 in the superimposed image. This substantializes a semiconductor failure analysis apparatus, analysis method, analysis program, and analysis system capable of securely and efficiently carrying out the analysis of the failure of the semiconductor device.

Abstract: A saddle riding type four-wheeled vehicle, suitable for rough terrain running, includes an engine having an electronically controlled fuel injection system. The vehicle also includes a throttle body disposed in back of a cylinder head of the engine. This configuration substantially protects the engine from drawing in mud, dust, and the like, and also eliminates the need for a protector of a throttle body. The fuel pump unit of the fuel injection system integrates the fuel pump, the fuel filter, and the pressure regulator into a single housing, to simplify the fuel piping required to connect different parts of the fuel supply system, as compared with conventional structures. This facilitates procedures of removing and installing the fuel tank and the fuel pump unit. The feature also reduces pumping loss of the fuel pump as well as parts cost.