Patents by Inventor Kazuhiro Mizutani

Kazuhiro Mizutani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10991071
    Abstract: An information processing apparatus includes a partial image generator configured to generate a partial image having a point-of-interest designated by a user, from a 360-degree image, a user interface (UI) unit configured to receive an indication of the point-of-interest via a UI screen for displaying the partial image, and a point-of-interest registering unit configured to register the point-of-interest, in response to a request from the user via the UI screen. The information processing apparatus also includes an interpolation line calculator configured to calculate an interpolation line for interpolating between a most recently registered point-of-interest and a current point-of-interest, and an interpolation line registering unit configured to register an interpolation line between the designated point-of-interest and a point-of-interest designated immediately prior to the designated point-of-interest.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: April 27, 2021
    Assignee: Ricoh Company, Ltd.
    Inventors: Kazuhiro Ohba, Keitaro Shimizu, Hitomi Mizutani, Tomohiko Sasaki, Tetsuyuki Osaki, Mitsuhiko Hirose
  • Patent number: 10818594
    Abstract: There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: October 27, 2020
    Assignee: UNITED SEMICONDUCTOR JAPAN CO., LTD.
    Inventors: Taiji Ema, Makoto Yasuda, Kazuhiro Mizutani
  • Publication number: 20190267320
    Abstract: There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.
    Type: Application
    Filed: May 10, 2019
    Publication date: August 29, 2019
    Applicant: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Taiji Ema, Makoto Yasuda, Kazuhiro Mizutani
  • Patent number: 10354953
    Abstract: There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: July 16, 2019
    Assignee: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Taiji Ema, Makoto Yasuda, Kazuhiro Mizutani
  • Publication number: 20180277478
    Abstract: There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.
    Type: Application
    Filed: May 31, 2018
    Publication date: September 27, 2018
    Applicant: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Taiji Ema, Makoto Yasuda, Kazuhiro Mizutani
  • Patent number: 10014254
    Abstract: There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: July 3, 2018
    Assignee: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Taiji Ema, Makoto Yasuda, Kazuhiro Mizutani
  • Publication number: 20170309561
    Abstract: There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.
    Type: Application
    Filed: July 12, 2017
    Publication date: October 26, 2017
    Applicant: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Taiji Ema, Makoto Yasuda, Kazuhiro Mizutani
  • Patent number: 9773733
    Abstract: There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: September 26, 2017
    Assignee: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Taiji Ema, Makoto Yasuda, Kazuhiro Mizutani
  • Publication number: 20160284720
    Abstract: There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.
    Type: Application
    Filed: March 10, 2016
    Publication date: September 29, 2016
    Inventors: Taiji Ema, Makoto Yasuda, Kazuhiro MIZUTANI
  • Patent number: 9388009
    Abstract: An objective of the present invention is to provide a sliding member for sheet-shaped recording material detachment having superior resistance to abrasion and superior heat resistant rigidity, and either a seal ring for an automobile or a seal ring or a sliding member for an industrial gas compressor, having high mechanical strength while ensuring flexibility. The objective is achieved with a sliding member for sheet-shaped recording material detachment, and either a seal ring for an automobile or a seal ring or a sliding member for an industrial gas compressor, made from a resin composite comprising: as a first element, either an adhesive fluorocarbon resin (A) or a resin compound of the resin (A) and a fluorocarbon resin (B) which differs from the resin (A), which are in a volumetric ratio (AB) of 5/95 to 99/1; and as a second element, 0.5 to 99 volume % of a thermoplastic polyimide (C).
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: July 12, 2016
    Assignees: ASAHI GLASS CO., LTD., STARLITE CO., LTD.
    Inventors: Eiichi Nishi, Takashi Sato, Hiroyoshi Uejima, Tomokazu Ichikawa, Toru Hashimoto, Shinya Kikutani, Kazuhiro Mizutani, Ryo Hisano
  • Patent number: 8912069
    Abstract: A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of active regions in the first and second areas; a first structure formed on an area from the active region in the first area to a nearby STI isolation region and having a first height; and a second structure formed on an area from the active region in the second area to a nearby STI isolation region and having a second height, wherein the surface of the said STI isolation region in the first area is lower than the surface of said STI isolation region in the second area.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: December 16, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Taiji Ema, Kazuhiro Mizutani
  • Patent number: 8896048
    Abstract: The present invention provides an apparatus and method for a metal oxide semiconductor field effect transistor (MOSFET) fabricated to reduce short channel effects. The MOSFET includes a semiconductor substrate, a gate stack formed above the semiconductor substrate, a drain side sidewall spacer formed on a drain side of the gate stack, a source side sidewall spacer formed on a source side of the gate stack, and source and drain regions. The source region is formed in the semiconductor substrate on the source side, and is aligned by the source side sidewall spacer to extend an effective channel length between the source region and drain region. The drain region is formed on the drain side in the semiconductor substrate, and is aligned by drain side sidewall spacer to further extend the effective channel length.
    Type: Grant
    Filed: June 4, 2004
    Date of Patent: November 25, 2014
    Assignee: Spansion LLC
    Inventors: Richard Fastow, Zhigang Wang, Yue-Song He, Kazuhiro Mizutani, Pavel Fastenko
  • Patent number: 8698253
    Abstract: A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of active regions in the first and second areas; a first structure formed on an area from the active region in the first area to a nearby STI isolation region and having a first height; and a second structure formed on an area from the active region in the second area to a nearby STI isolation region and having a second height, wherein the surface of the said STI isolation region in the first area is lower than the surface of said STI isolation region in the second area.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: April 15, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Taiji Ema, Kazuhiro Mizutani
  • Publication number: 20130313774
    Abstract: An objective of the present invention is to provide a sliding member for sheet-shaped recording material detachment having superior resistance to abrasion and superior heat resistant rigidity, and either a seal ring for an automobile or a seal ring or a sliding member for an industrial gas compressor, having high mechanical strength while ensuring flexibility. The objective is achieved with a sliding member for sheet-shaped recording material detachment, and either a seal ring for an automobile or a seal ring or a sliding member for an industrial gas compressor, made from a resin composite comprising: as a first element, either an adhesive fluorocarbon resin (A) or a resin compound of the resin (A) and a fluorocarbon resin (B) which differs from the resin (A), which are in a volumetric ratio (AB) of 5/95 to 99/1; and as a second element, 0.5 to 99 volume % of a thermoplastic polyimide (C).
    Type: Application
    Filed: November 10, 2011
    Publication date: November 28, 2013
    Applicants: STARLITE CO., LTD., ASAHI GLASS CO., LTD.
    Inventors: Eiichi Nishi, Takashi Sato, Hiroyoshi Uejima, Tomokazu Ichikawa, Toru Hashimoto, Shinya Kikutani, Kazuhiro Mizutani, Ryo Hisano
  • Publication number: 20130299892
    Abstract: A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of active regions in the first and second areas; a first structure formed on an area from the active region in the first area to a nearby STI isolation region and having a first height; and a second structure formed on an area from the active region in the second area to a nearby STI isolation region and having a second height, wherein the surface of the said STI isolation region in the first area is lower than the surface of said STI isolation region in the second area.
    Type: Application
    Filed: July 15, 2013
    Publication date: November 14, 2013
    Inventors: Taiji Ema, Kazuhiro Mizutani
  • Publication number: 20130302967
    Abstract: A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of active regions in the first and second areas; a first structure formed on an area from the active region in the first area to a nearby STI isolation region and having a first height; and a second structure formed on an area from the active region in the second area to a nearby STI isolation region and having a second height, wherein the surface of the said STI isolation region in the first area is lower than the surface of said STI isolation region in the second area.
    Type: Application
    Filed: July 15, 2013
    Publication date: November 14, 2013
    Inventors: Taiji Ema, Kazuhiro Mizutani
  • Patent number: 8503234
    Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: August 6, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Satoshi Torii, Kazuhiro Mizutani, Toshio Nomura, Masayoshi Asano, Ikuto Fukuoka, Hiroshi Mawatari, Motoi Takahashi
  • Patent number: 8497176
    Abstract: A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of active regions in the first and second areas; a first structure formed on an area from the active region in the first area to a nearby STI isolation region and having a first height; and a second structure formed on an area from the active region in the second area to a nearby STI isolation region and having a second height, wherein the surface of the said STI isolation region in the first area is lower than the surface of said STI isolation region in the second area.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: July 30, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Taiji Ema, Kazuhiro Mizutani
  • Patent number: 8400828
    Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: March 19, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Satoshi Torii, Kazuhiro Mizutani, Toshio Nomura, Masayoshi Asano, Ikuto Fukuoka, Hiroshi Mawatari, Motoi Takahashi
  • Patent number: 8237210
    Abstract: A semiconductor apparatus is presented that includes an array of memory cells. The memory cells are arranged in rows and columns. Non-intersecting shallow trench isolation regions isolate the columns of memory cells. Also included is at least one source region that is isolated between an adjoining pair of the non-intersecting shallow trench isolation regions and isolated from a drain region. The source region is coupled to source lines in the array of memory cells. A contact couples a select plurality of the columns of memory cells, the select plurality functioning as a single content addressable memory cell.
    Type: Grant
    Filed: February 8, 2006
    Date of Patent: August 7, 2012
    Assignee: Spansion LLC
    Inventors: Zhigang Wang, Kazuhiro Mizutani, Richard Fastow