Patents by Inventor Kazuhiro Mizutani
Kazuhiro Mizutani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11926246Abstract: In a local cart traveling system, a frame track includes first and second metal rails each with an L-shaped cross section and facing each other. A local cart is within the frame track, and includes a first electricity receiving tire and a second electricity receiving tire to travel on horizontal travel surfaces of the rails. A voltage supplier supplies an AC voltage to the travel surfaces, so that the first metal rail and a first electricity receiving tire define a first capacitor and the second metal rail and the second electricity receiving tire define a second capacitor. The local cart includes a power receiver to receive AC power, and a travel motor that receives power after the AC power is rectified. The frame track includes a connecting plate as an electrical insulator covering portions of the surfaces of vertical walls of the first metal rail and the second metal rail.Type: GrantFiled: June 1, 2018Date of Patent: March 12, 2024Assignees: MURATA MACHINERY, LTD., NATIONAL UNIVERSITY CORPORATION TOYOHASHI UNIVERSITY OF TECHNOLOGYInventors: Minoru Mizutani, Kazuhiro Ishikawa, Masafumi Hayakawa, Takashi Ohira, Naoki Sakai, Hiroki Kuniyoshi, Makoto Teramoto
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Patent number: 10818594Abstract: There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.Type: GrantFiled: May 10, 2019Date of Patent: October 27, 2020Assignee: UNITED SEMICONDUCTOR JAPAN CO., LTD.Inventors: Taiji Ema, Makoto Yasuda, Kazuhiro Mizutani
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Publication number: 20190267320Abstract: There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.Type: ApplicationFiled: May 10, 2019Publication date: August 29, 2019Applicant: MIE FUJITSU SEMICONDUCTOR LIMITEDInventors: Taiji Ema, Makoto Yasuda, Kazuhiro Mizutani
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Patent number: 10354953Abstract: There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.Type: GrantFiled: May 31, 2018Date of Patent: July 16, 2019Assignee: MIE FUJITSU SEMICONDUCTOR LIMITEDInventors: Taiji Ema, Makoto Yasuda, Kazuhiro Mizutani
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Publication number: 20180277478Abstract: There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.Type: ApplicationFiled: May 31, 2018Publication date: September 27, 2018Applicant: MIE FUJITSU SEMICONDUCTOR LIMITEDInventors: Taiji Ema, Makoto Yasuda, Kazuhiro Mizutani
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Patent number: 10014254Abstract: There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.Type: GrantFiled: July 12, 2017Date of Patent: July 3, 2018Assignee: MIE FUJITSU SEMICONDUCTOR LIMITEDInventors: Taiji Ema, Makoto Yasuda, Kazuhiro Mizutani
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Publication number: 20170309561Abstract: There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.Type: ApplicationFiled: July 12, 2017Publication date: October 26, 2017Applicant: MIE FUJITSU SEMICONDUCTOR LIMITEDInventors: Taiji Ema, Makoto Yasuda, Kazuhiro Mizutani
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Patent number: 9773733Abstract: There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.Type: GrantFiled: March 10, 2016Date of Patent: September 26, 2017Assignee: MIE FUJITSU SEMICONDUCTOR LIMITEDInventors: Taiji Ema, Makoto Yasuda, Kazuhiro Mizutani
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Publication number: 20160284720Abstract: There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.Type: ApplicationFiled: March 10, 2016Publication date: September 29, 2016Inventors: Taiji Ema, Makoto Yasuda, Kazuhiro MIZUTANI
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Patent number: 9388009Abstract: An objective of the present invention is to provide a sliding member for sheet-shaped recording material detachment having superior resistance to abrasion and superior heat resistant rigidity, and either a seal ring for an automobile or a seal ring or a sliding member for an industrial gas compressor, having high mechanical strength while ensuring flexibility. The objective is achieved with a sliding member for sheet-shaped recording material detachment, and either a seal ring for an automobile or a seal ring or a sliding member for an industrial gas compressor, made from a resin composite comprising: as a first element, either an adhesive fluorocarbon resin (A) or a resin compound of the resin (A) and a fluorocarbon resin (B) which differs from the resin (A), which are in a volumetric ratio (AB) of 5/95 to 99/1; and as a second element, 0.5 to 99 volume % of a thermoplastic polyimide (C).Type: GrantFiled: November 10, 2011Date of Patent: July 12, 2016Assignees: ASAHI GLASS CO., LTD., STARLITE CO., LTD.Inventors: Eiichi Nishi, Takashi Sato, Hiroyoshi Uejima, Tomokazu Ichikawa, Toru Hashimoto, Shinya Kikutani, Kazuhiro Mizutani, Ryo Hisano
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Patent number: 8912069Abstract: A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of active regions in the first and second areas; a first structure formed on an area from the active region in the first area to a nearby STI isolation region and having a first height; and a second structure formed on an area from the active region in the second area to a nearby STI isolation region and having a second height, wherein the surface of the said STI isolation region in the first area is lower than the surface of said STI isolation region in the second area.Type: GrantFiled: July 15, 2013Date of Patent: December 16, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Taiji Ema, Kazuhiro Mizutani
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Patent number: 8896048Abstract: The present invention provides an apparatus and method for a metal oxide semiconductor field effect transistor (MOSFET) fabricated to reduce short channel effects. The MOSFET includes a semiconductor substrate, a gate stack formed above the semiconductor substrate, a drain side sidewall spacer formed on a drain side of the gate stack, a source side sidewall spacer formed on a source side of the gate stack, and source and drain regions. The source region is formed in the semiconductor substrate on the source side, and is aligned by the source side sidewall spacer to extend an effective channel length between the source region and drain region. The drain region is formed on the drain side in the semiconductor substrate, and is aligned by drain side sidewall spacer to further extend the effective channel length.Type: GrantFiled: June 4, 2004Date of Patent: November 25, 2014Assignee: Spansion LLCInventors: Richard Fastow, Zhigang Wang, Yue-Song He, Kazuhiro Mizutani, Pavel Fastenko
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Patent number: 8698253Abstract: A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of active regions in the first and second areas; a first structure formed on an area from the active region in the first area to a nearby STI isolation region and having a first height; and a second structure formed on an area from the active region in the second area to a nearby STI isolation region and having a second height, wherein the surface of the said STI isolation region in the first area is lower than the surface of said STI isolation region in the second area.Type: GrantFiled: July 15, 2013Date of Patent: April 15, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Taiji Ema, Kazuhiro Mizutani
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Publication number: 20130313774Abstract: An objective of the present invention is to provide a sliding member for sheet-shaped recording material detachment having superior resistance to abrasion and superior heat resistant rigidity, and either a seal ring for an automobile or a seal ring or a sliding member for an industrial gas compressor, having high mechanical strength while ensuring flexibility. The objective is achieved with a sliding member for sheet-shaped recording material detachment, and either a seal ring for an automobile or a seal ring or a sliding member for an industrial gas compressor, made from a resin composite comprising: as a first element, either an adhesive fluorocarbon resin (A) or a resin compound of the resin (A) and a fluorocarbon resin (B) which differs from the resin (A), which are in a volumetric ratio (AB) of 5/95 to 99/1; and as a second element, 0.5 to 99 volume % of a thermoplastic polyimide (C).Type: ApplicationFiled: November 10, 2011Publication date: November 28, 2013Applicants: STARLITE CO., LTD., ASAHI GLASS CO., LTD.Inventors: Eiichi Nishi, Takashi Sato, Hiroyoshi Uejima, Tomokazu Ichikawa, Toru Hashimoto, Shinya Kikutani, Kazuhiro Mizutani, Ryo Hisano
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Publication number: 20130299892Abstract: A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of active regions in the first and second areas; a first structure formed on an area from the active region in the first area to a nearby STI isolation region and having a first height; and a second structure formed on an area from the active region in the second area to a nearby STI isolation region and having a second height, wherein the surface of the said STI isolation region in the first area is lower than the surface of said STI isolation region in the second area.Type: ApplicationFiled: July 15, 2013Publication date: November 14, 2013Inventors: Taiji Ema, Kazuhiro Mizutani
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Publication number: 20130302967Abstract: A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of active regions in the first and second areas; a first structure formed on an area from the active region in the first area to a nearby STI isolation region and having a first height; and a second structure formed on an area from the active region in the second area to a nearby STI isolation region and having a second height, wherein the surface of the said STI isolation region in the first area is lower than the surface of said STI isolation region in the second area.Type: ApplicationFiled: July 15, 2013Publication date: November 14, 2013Inventors: Taiji Ema, Kazuhiro Mizutani
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Patent number: 8503234Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.Type: GrantFiled: July 22, 2011Date of Patent: August 6, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Satoshi Torii, Kazuhiro Mizutani, Toshio Nomura, Masayoshi Asano, Ikuto Fukuoka, Hiroshi Mawatari, Motoi Takahashi
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Patent number: 8497176Abstract: A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of active regions in the first and second areas; a first structure formed on an area from the active region in the first area to a nearby STI isolation region and having a first height; and a second structure formed on an area from the active region in the second area to a nearby STI isolation region and having a second height, wherein the surface of the said STI isolation region in the first area is lower than the surface of said STI isolation region in the second area.Type: GrantFiled: June 20, 2011Date of Patent: July 30, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Taiji Ema, Kazuhiro Mizutani
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Patent number: 8400828Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.Type: GrantFiled: March 30, 2012Date of Patent: March 19, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Satoshi Torii, Kazuhiro Mizutani, Toshio Nomura, Masayoshi Asano, Ikuto Fukuoka, Hiroshi Mawatari, Motoi Takahashi
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Patent number: 8237210Abstract: A semiconductor apparatus is presented that includes an array of memory cells. The memory cells are arranged in rows and columns. Non-intersecting shallow trench isolation regions isolate the columns of memory cells. Also included is at least one source region that is isolated between an adjoining pair of the non-intersecting shallow trench isolation regions and isolated from a drain region. The source region is coupled to source lines in the array of memory cells. A contact couples a select plurality of the columns of memory cells, the select plurality functioning as a single content addressable memory cell.Type: GrantFiled: February 8, 2006Date of Patent: August 7, 2012Assignee: Spansion LLCInventors: Zhigang Wang, Kazuhiro Mizutani, Richard Fastow