Patents by Inventor Kazuhiro Ohba

Kazuhiro Ohba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11522132
    Abstract: A storage device includes a first electrode, a second electrode, and a storage layer. The second electrode is disposed to oppose the first electrode. The storage layer is provided between the first electrode and the second electrode, and includes one or more chalcogen elements selected from tellurium (Te), selenium (Se), and sulfur (S), transition metal, and oxygen. The storage layer has a non-linear resistance characteristic, and the storage layer is caused to be in a low-resistance state by setting an application voltage to be equal to or higher than a predetermined threshold voltage and is caused to be in a high-resistance state by setting the application voltage to be lower than the predetermined threshold voltage to thereby have a rectification characteristic.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: December 6, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Kazuhiro Ohba, Seiji Nonoguchi, Hiroaki Sei, Takeyuki Sone, Minoru Ikarashi
  • Patent number: 11462685
    Abstract: A switch device according to an embodiment of the present disclosure includes a first electrode; a second electrode opposed to the first electrode; and a switch layer including selenium (Se), at least one kind of germanium (Ge) or silicon (Si), boron (B), carbon (C), (Ga), and arsenic (As), and provided between the first electrode and the second electrode.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: October 4, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hiroaki Sei, Kazuhiro Ohba, Shuichiro Yasuda
  • Publication number: 20220162742
    Abstract: Provided are a sputtering target that makes it possible to form a chalcogenide material film with enhanced heat resistance, a method of manufacturing the sputtering target, and a memory device manufacturing method. The sputtering target includes an alloy containing a first component containing arsenic and selenium and a second component containing at least one of boron and carbon.
    Type: Application
    Filed: March 13, 2020
    Publication date: May 26, 2022
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Kazuhiro OHBA, Shuichiro YASUDA, Hiroaki SEI, Katsuhisa ARATANI
  • Patent number: 11195295
    Abstract: A control system of performing an analysis in a specific space comprising circuitry configured to receive image data corresponding to captured image captured and transmitted from an image capturing device, store, in a memory, the received image data and coordinates of a movable object that indicate a position of the movable object included in the image data in association with each other, the movable object being one or more movable objects, in response to displaying an image generated from the stored image data on a display, receive an input for setting a specific closed region in the image displayed on the display, and measure the movable object within the specific closed region in the image based on coordinates of the specific closed region set by the received input, and the stored coordinates of the movable object.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: December 7, 2021
    Assignee: RICOH COMPANY, LTD.
    Inventors: Takafumi Shimmoto, Kazuhiro Ohba
  • Patent number: 11183633
    Abstract: A switch device includes: a first electrode; a second electrode opposed to the first electrode; and a switch layer provided between the first electrode and the second electrode, and the switch layer includes one or more kinds of chalcogen elements selected from tellurium (Te), selenium (Se), and sulfur (S) and one or more kinds of first elements selected from phosphorus (P) and arsenic (As), and further includes one or both of one or more kinds of second elements selected from boron (B) and carbon (C) and one or more kinds of third elements selected from aluminum (Al), gallium (Ga), and indium (In).
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: November 23, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hiroaki Sei, Kazuhiro Ohba, Takeyuki Sone, Seiji Nonoguchi, Minoru Ikarashi
  • Patent number: 11152428
    Abstract: There is provided a selection device that includes a first electrode, a second electrode opposed to the first electrode, a semiconductor layer provided between the first electrode and the second electrode, and including at least one kind of chalcogen element selected from tellurium (Te), selenium (Se), and sulfur (S), and at least one kind of first element selected from boron (B), aluminum (Al), gallium (Ga), phosphorus (P), arsenic (As), carbon (C), germanium (Ge), and silicon (Si), and a first heat bypass layer provided at least in a portion around the semiconductor layer between the first electrode and the second electrode and having higher thermal conductivity than the semiconductor layer.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: October 19, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Minoru Ikarashi, Takeyuki Sone, Seiji Nonoguchi, Hiroaki Sei, Kazuhiro Ohba
  • Patent number: 11018189
    Abstract: A storage apparatus includes a plurality of first wiring layers extending in one direction, a plurality of second wiring layers extending in another direction, and a plurality of memory cells provided in respective opposing regions in which the plurality of first wiring layers and the plurality of second wiring layers are opposed to each other. The plurality of memory cells each includes a selector element layer, a storage element layer, and an intermediate electrode layer provided between the selector element layer and the storage element layer. One or more of the selector element layer, the storage element layer, and the intermediate electrode layer is a common layer that is common between the plurality of memory cells, in which the plurality of memory cells is adjacent to each other and extends in the one direction or the other direction. The intermediate electrode layer includes a nonlinear resistive material.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: May 25, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Seiji Nonoguchi, Katsuhisa Aratani, Kazuhiro Ohba
  • Patent number: 11004902
    Abstract: Provided is a circuit element that includes paired inert electrodes, and a switch layer provided between the paired inert electrodes, that functions as a selection element and a storage element as a single layer, and having a differential negative resistance region in a current-voltage characteristic.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: May 11, 2021
    Assignee: SONY CORPORATION
    Inventors: Minoru Ikarashi, Seiji Nonoguchi, Takeyuki Sone, Hiroaki Sei, Kazuhiro Ohba, Jun Okuno
  • Patent number: 10991071
    Abstract: An information processing apparatus includes a partial image generator configured to generate a partial image having a point-of-interest designated by a user, from a 360-degree image, a user interface (UI) unit configured to receive an indication of the point-of-interest via a UI screen for displaying the partial image, and a point-of-interest registering unit configured to register the point-of-interest, in response to a request from the user via the UI screen. The information processing apparatus also includes an interpolation line calculator configured to calculate an interpolation line for interpolating between a most recently registered point-of-interest and a current point-of-interest, and an interpolation line registering unit configured to register an interpolation line between the designated point-of-interest and a point-of-interest designated immediately prior to the designated point-of-interest.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: April 27, 2021
    Assignee: Ricoh Company, Ltd.
    Inventors: Kazuhiro Ohba, Keitaro Shimizu, Hitomi Mizutani, Tomohiko Sasaki, Tetsuyuki Osaki, Mitsuhiko Hirose
  • Patent number: 10971685
    Abstract: A selective device includes a first electrode, a second electrode, a switch device, and a non-linear resistive device. The second electrode is disposed to face the first electrode. The switch device is provided between the first electrode and the second electrode. The non-linear resistive device contains one or more of boron (B), silicon (Si), and carbon (C). The non-linear resistive device is coupled to the switch device in series.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: April 6, 2021
    Assignee: SONY CORPORATION
    Inventors: Kazuhiro Ohba, Minoru Ikarashi
  • Publication number: 20210036221
    Abstract: A switching device according to an embodiment of the present disclosure includes: a first electrode; a second electrode disposed to be opposed to the first electrode; and a switching layer provided between the first electrode and the second electrode. The switching layer includes at least one chalcogen element selected from sulfur (S), selenium (Se), and tellurium (Te). At least one of the first electrode or the second electrode includes carbon (C) and, as an additive element, at least one of germanium (Ge), phosphorus (P), or arsenic (As).
    Type: Application
    Filed: March 14, 2019
    Publication date: February 4, 2021
    Inventors: KAZUHIRO OHBA, HIROAKI SEI, SHUICHIRO YASUDA
  • Publication number: 20200411759
    Abstract: A switch device according to an embodiment of the present disclosure includes a first electrode; a second electrode opposed to the first electrode; and a switch layer including selenium (Se), at least one kind of germanium (Ge) or silicon (Si), boron (B), carbon (C), (Ga), and arsenic (As), and provided between the first electrode and the second electrode.
    Type: Application
    Filed: January 31, 2019
    Publication date: December 31, 2020
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hiroaki SEI, Kazuhiro OHBA, Shuichiro YASUDA
  • Patent number: 10879312
    Abstract: There are provided a memory device and a memory unit that make it possible to improve retention property of a resistance value in low-current writing. The memory device of the technology includes a first electrode, a memory layer, and a second electrode in order, in which the memory layer includes an ion source layer containing one or more transition metal elements selected from group 4, group 5, and group 6 in periodic table, one or more chalcogen elements selected from tellurium (Te), sulfur (S), and selenium (Se), and one or both of boron (B) and carbon (C), and a resistance change layer having resistance that is varied by voltage application to the first electrode and the second electrode.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: December 29, 2020
    Assignee: SONY CORPORATION
    Inventors: Hiroaki Sei, Kazuhiro Ohba, Seiji Nonoguchi
  • Publication number: 20200350498
    Abstract: A storage device includes a first electrode, a second electrode, and a storage layer. The second electrode is disposed to oppose the first electrode. The storage layer is provided between the first electrode and the second electrode, and includes one or more chalcogen elements selected from tellurium (Te), selenium (Se), and sulfur (S), transition metal, and oxygen. The storage layer has a non-linear resistance characteristic, and the storage layer is caused to be in a low-resistance state by setting an application voltage to be equal to or higher than a predetermined threshold voltage and is caused to be in a high-resistance state by setting the application voltage to be lower than the predetermined threshold voltage to thereby have a rectification characteristic.
    Type: Application
    Filed: December 6, 2018
    Publication date: November 5, 2020
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Kazuhiro OHBA, Seiji NONOGUCHI, Hiroaki SEI, Takeyuki SONE, Minoru IKARASHI
  • Patent number: 10804321
    Abstract: A switch device according to an embodiment of the technology includes a first electrode, a second electrode that is disposed to face the first electrode, and a switch layer that is provided between the first electrode and the second electrode. The switch layer contains a chalcogen element. The switch layer includes a first region and a second region which have different composition ratios of one or more of chalcogen elements or different types of the one or more of chalcogen elements. The first region is provided close to the first electrode. The second region is provided closer to the second electrode than the first region.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: October 13, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Kazuhiro Ohba, Hiroaki Sei, Seiji Nonoguchi, Takeyuki Sone, Minoru Ikarashi
  • Publication number: 20200167948
    Abstract: A control system of performing an analysis in a specific space comprising circuitry configured to receive image data corresponding to captured image captured and transmitted from an image capturing device, store, in a memory, the received image data and coordinates of a movable object that indicate a position of the movable object included in the image data in association with each other, the movable object being one or more movable objects, in response to displaying an image generated from the stored image data on a display, receive an input for setting a specific closed region in the image displayed on the display, and measure the movable object within the specific closed region in the image based on coordinates of the specific closed region set by the received input, and the stored coordinates of the movable object.
    Type: Application
    Filed: November 12, 2019
    Publication date: May 28, 2020
    Inventors: Takafumi SHIMMOTO, Kazuhiro OHBA
  • Publication number: 20200052036
    Abstract: A selection device according to an embodiment of the present disclosure includes: a first electrode; a second electrode opposed to the first electrode; a semiconductor layer provided between the first electrode and the second electrode, and including at least one kind of chalcogen element selected from tellurium (Te), selenium (Se), and sulfur (S), and at least one kind of first element selected from boron (B), aluminum (Al), gallium (Ga), phosphorus (P), arsenic (As), carbon (C), germanium (Ge), and silicon (Si); and a first heat bypass layer provided at least in a portion around the semiconductor layer between the first electrode and the second electrode and having higher thermal conductivity than the semiconductor layer.
    Type: Application
    Filed: April 6, 2018
    Publication date: February 13, 2020
    Inventors: MINORU IKARASHI, TAKEYUKI SONE, SEIJI NONOGUCHI, HIROAKI SEI, KAZUHIRO OHBA
  • Publication number: 20200052040
    Abstract: A storage apparatus according to an embodiment of the present disclosure includes a plurality of first wiring layers extending in one direction, a plurality of second wiring layers extending in another direction, and a plurality of memory cells provided in respective opposing regions in which the plurality of first wiring layers and the plurality of second wiring layers are opposed to each other. The plurality of memory cells each includes a selector element layer, a storage element layer, and an intermediate electrode layer provided between the selector element layer and the storage element layer. One or more of the selector element layer, the storage element layer, and the intermediate electrode layer is a common layer that is common between the plurality of memory cells, in which the plurality of memory cells is adjacent to each other and extends in the one direction or the other direction. The intermediate electrode layer includes a nonlinear resistive material.
    Type: Application
    Filed: March 15, 2018
    Publication date: February 13, 2020
    Inventors: SEIJI NONOGUCHI, KATSUHISA ARATANI, KAZUHIRO OHBA
  • Patent number: 10529777
    Abstract: A switch device according to an embodiment of the technology includes a first electrode, a second electrode that faces the first electrode, and a switch layer provided between the first electrode and the second electrode. The switch layer includes a chalcogen element. The switch device further includes a diffusion suppressing layer that is in contact with at least a portion of a surface of the switch layer, and suppresses diffusion of oxygen into the switch layer.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: January 7, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Hiroaki Sei, Kazuhiro Ohba
  • Publication number: 20190371859
    Abstract: There are provided a memory device and a memory unit that make it possible to improve retention property of a resistance value in low-current writing. The memory device of the technology includes a first electrode, a memory layer, and a second electrode in order, in which the memory layer includes an ion source layer containing one or more transition metal elements selected from group 4, group 5, and group 6 in periodic table, one or more chalcogen elements selected from tellurium (Te), sulfur (S), and selenium (Se), and one or both of boron (B) and carbon (C), and a resistance change layer having resistance that is varied by voltage application to the first electrode and the second electrode.
    Type: Application
    Filed: August 8, 2019
    Publication date: December 5, 2019
    Inventors: HIROAKI SEI, KAZUHIRO OHBA, SEIJI NONOGUCHI