Patents by Inventor Kazuhiro Ohnishi
Kazuhiro Ohnishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8004041Abstract: A semiconductor device for surge protection having high surge resistance is provided.Type: GrantFiled: August 24, 2005Date of Patent: August 23, 2011Assignee: Panasonic CorporationInventor: Kazuhiro Ohnishi
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Publication number: 20090034143Abstract: A semiconductor device for surge protection having high surge resistance is provided.Type: ApplicationFiled: August 24, 2005Publication date: February 5, 2009Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventor: Kazuhiro Ohnishi
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Patent number: 7238582Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.Type: GrantFiled: December 1, 2004Date of Patent: July 3, 2007Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Hiromi Shimamoto, Takashi Uchino, Takeo Shiba, Kazuhiro Ohnishi, Yoichi Tamaki, Takashi Kobayashi, Toshiyuki Kikuchi, Takahide Ikeda
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Patent number: 7042051Abstract: Provided is a manufacturing method of a semiconductor device which comprises forming, all over the surface of a substrate below the channel region of a MISFET, a p type impurity layer having a first peak in impurity concentration distribution and another p type impurity layer having a second peak in impurity concentration distribution, each layer having a function of preventing punch-through. Compared with a device having a punch through stopper layer of a pocket structure, the device of the present invention is suppressed in fluctuations in the threshold voltage. Moreover, with a relative increase in the controllable width of a depletion layer, a sub-threshold swing becomes small, thereby making it possible to prevent lowering of the threshold voltage and to improve a switching rate of the MISFET.Type: GrantFiled: November 19, 2002Date of Patent: May 9, 2006Assignee: Renesas Technology Corp.Inventors: Fumio Ootsuka, Takahiro Onai, Kazuhiro Ohnishi, Shoji Wakahara
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Patent number: 7029988Abstract: A method and device are provided for shallow trench isolation for a silicon wafer containing silicon-germanium. In one example, the method comprises forming a trench region in a silicon-germanium layer of a semiconductor substrate containing a single crystal silicon-germanium layer on the surface; forming a first single crystal silicon layer in the trench region and an active region; oxidizing the first single crystal silicon layer; forming a first thermal oxide layer on the surface of the first single crystal silicon layer; forming a device isolation region; embedding an insulator in the trench region; and forming a device in an active region over the single crystal silicon-germanium layer separated by the device isolation region, wherein the step of forming the device in the active region further includes forming a doped region of a depth to reach within the single crystal silicon-germanium layer below the first single crystal silicon layer.Type: GrantFiled: September 9, 2004Date of Patent: April 18, 2006Assignee: Renesas Technology CorporationInventors: Kazuhiro Ohnishi, Nobuyuki Sugii, Takahiro Onai
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Patent number: 6936875Abstract: With the invention, it is possible to avoid deterioration in short-channel characteristics, caused by a silicon germanium layer coming into contact with the channel of a strained SOI transistor. Further, it is possible to fabricate a double-gate type of strained SOI transistor or to implement mixedly mounting the strained SOI transistor and a conventional silicon or SOI transistor on the same wafer. According to the invention, for example, a strained silicon layer is grown on a strain-relaxed silicon germanium layer, and subsequently, portions of the silicon germanium layer are removed, thereby constituting a channel layer in the strained silicon layer.Type: GrantFiled: September 30, 2003Date of Patent: August 30, 2005Assignee: Renesas Technology Corp.Inventors: Nobuyuki Sugii, Kazuhiro Ohnishi, Katsuyoshi Washio
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Publication number: 20050173738Abstract: Provided is a technology capable of reducing the on-resistance of a power MISFET while suppressing the generation of defects in a strained silicon layer. A strained silicon layer is formed only over an underlying strained silicon layer in the drain region by epitaxial growth. Large portions of a lightly-doped n type impurity diffusion region, offset region and heavily-doped n type impurity diffusion region are formed in these strained silicon layers, having a higher electron mobility than a conventional silicon layer.Type: ApplicationFiled: February 4, 2005Publication date: August 11, 2005Inventors: Masao Kondo, Yutaka Hoshino, Kazuhiro Ohnishi, Isao Yoshida, Masatoshi Morikawa
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Publication number: 20050164441Abstract: Process for producing a semiconductor device includes forming an insulation layer on a semiconductor substrate surface and depositing a silicon layer on the insulation layer, a reaction barrier layer such as a metal nitride layer on the first metallic layer and a second metallic layer on the barrier layer, processing a stacked structure of the silicon layer, first metallic layer, barrier layer and second metallic layer to form a gate electrode, using the gate electrode as a mask and doping an impurity into the surface of the semiconductor substrate to form active regions of the device, heat reacting the first metallic layer with the silicon layer to form a metal silicide layer between the reaction barrier layer and the silicon layer. The heat reaction process effected may be performed prior to or after the formation of the gate electrode. The metal silicide film may be a deposited film.Type: ApplicationFiled: March 24, 2005Publication date: July 28, 2005Inventors: Kazuhiro Ohnishi, Naoki Yamamoto
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Publication number: 20050101097Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.Type: ApplicationFiled: December 1, 2004Publication date: May 12, 2005Inventors: Hiromi Shimamoto, Takashi Uchino, Takeo Shiba, Kazuhiro Ohnishi, Yoichi Tamaki, Takashi Kobayashi, Toshiyuki Kikuchi, Takahide Ikeda
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Patent number: 6878606Abstract: A method and device are provided for shallow trench isolation for a silicon wafer containing silicon-germanium. In one example, the method comprises forming a trench region in a silicon-germanium layer of a semiconductor substrate containing a single crystal silicon-germanium layer on the surface; forming a first single crystal silicon layer in the trench region and an active region; oxidizing the first single crystal silicon layer; forming a first thermal oxide layer on the surface of the first single crystal silicon layer; forming a device isolation region; embedding an insulator in the trench region; and forming a device in an active region over the single crystal silicon-germanium layer separated by the device isolation region, wherein the step of forming the device in the active region further includes forming a doped region of a depth to reach within the single crystal silicon-germanium layer below the first single crystal silicon layer.Type: GrantFiled: May 28, 2003Date of Patent: April 12, 2005Assignee: Renesas Technology Corp.Inventors: Kazuhiro Ohnishi, Nobuyuki Sugii, Takahiro Onai
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Publication number: 20050032327Abstract: A method and device are provided for shallow trench isolation for a silicon wafer containing silicon-germanium. In one example, the method comprises forming a trench region in a silicon-germanium layer of a semiconductor substrate containing a single crystal silicon-germanium layer on the surface; forming a first single crystal silicon layer in the trench region and an active region; oxidizing the first single crystal silicon layer; forming a first thermal oxide layer on the surface of the first single crystal silicon layer; forming a device isolation region; embedding an insulator in the trench region; and forming a device in an active region over the single crystal silicon-germanium layer separated by the device isolation region, wherein the step of forming the device in the active region further includes forming a doped region of a depth to reach within the single crystal silicon-germanium layer below the first single crystal silicon layer.Type: ApplicationFiled: September 9, 2004Publication date: February 10, 2005Inventors: Kazuhiro Ohnishi, Nobuyuki Sugii, Takahiro Onai
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Patent number: 6835632Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.Type: GrantFiled: June 13, 2003Date of Patent: December 28, 2004Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Hiromi Shimamoto, Takashi Uchino, Takeo Shiba, Kazuhiro Ohnishi, Yoichi Tamaki, Takashi Kobayashi, Toshiyuki Kikuchi, Takahide Ikeda
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Publication number: 20040178440Abstract: Process for producing a semiconductor device includes forming an insulation layer on a semiconductor substrate surface and depositing a silicon layer on the insulation layer, a reaction barrier layer such as a metal nitride layer on the first metallic layer and a second metallic layer on the barrier layer, processing a stacked structure of the silicon layer, first metallic layer, barrier layer and second metallic layer to form a gate electrode, using the gate electrode as a mask and doping an impurity into the surface of the semiconductor substrate to form active regions of the device, heat reacting the first metallic layer with the silicon layer to form a metal silicide layer between the reaction barrier layer and the silicon layer. The heat reaction process effected may be performed prior to or after the formation of the gate electrode. The metal silicide film may be a deposited film.Type: ApplicationFiled: March 31, 2004Publication date: September 16, 2004Inventors: Kazuhiro Ohnishi, Naoki Yamamoto
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Publication number: 20040121554Abstract: A method and device are provided for shallow trench isolation for a silicon wafer containing silicon-germanium. In one example, the method comprises forming a trench region in a silicon-germanium layer of a semiconductor substrate containing a single crystal silicon-germanium layer on the surface; forming a first single crystal silicon layer in the trench region and an active region; oxidizing the first single crystal silicon layer; forming a first thermal oxide layer on the surface of the first single crystal silicon layer; forming a device isolation region; embedding an insulator in the trench region; and forming a device in an active region over the single crystal silicon-germanium layer separated by the device isolation region, wherein the step of forming the device in the active region further includes forming a doped region of a depth to reach within the single crystal silicon-germanium layer below the first single crystal silicon layer.Type: ApplicationFiled: May 28, 2003Publication date: June 24, 2004Applicant: Hitachi, Ltd.Inventors: Kazuhiro Ohnishi, Nobuyuki Sugii, Takahiro Onai
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Patent number: 6750503Abstract: A semiconductor device with an MOS transistor gate electrode in a stacked structure comprising a silicon layer, a metal silicide layer, a reaction barrier layer such as a metal nitride layer and a metallic layer formed from the bottom upwards has an increased circuit performance owing to a gate resistance-reducing effect.Type: GrantFiled: April 11, 2001Date of Patent: June 15, 2004Assignee: Renesas Technology Corp.Inventors: Kazuhiro Ohnishi, Naoki Yamamoto
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Publication number: 20040108559Abstract: With the invention, it is possible to avoid deterioration in short-channel characteristics, caused by a silicon germanium layer coming into contact with the channel of a strained SOI transistor. Further, it is possible to fabricate a double-gate type of strained SOI transistor or to implement mixedly mounting the strained SOI transistor and a conventional silicon or SOI transistor on the same wafer. According to the invention, for example, a strained silicon layer is grown on a strain-relaxed silicon germanium layer, and subsequently, portions of the silicon germanium layer are removed, thereby constituting a channel layer in the strained silicon layer.Type: ApplicationFiled: September 30, 2003Publication date: June 10, 2004Applicant: Renesas Technology Corp.Inventors: Nobuyuki Sugii, Kazuhiro Ohnishi, Katsuyoshi Washio
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Publication number: 20030227062Abstract: Source-drain diffusion regions of a shallow junction and a stacked metal silicide film structure of a low resistance in a miniaturized MIS transistor are to be attained while ensuring high reliability. The concentration of an impurity (As, P, In, Sb) in surface areas of source-drain diffusion regions (6, 7) is set to a value of not smaller than 5×1021/cm3. Alternatively, an alloy film of germanium and silicon containing not less than 20% of germanium, or germanium film, is formed on surface areas of the source-drain diffusion regions (6, 7).Type: ApplicationFiled: June 6, 2003Publication date: December 11, 2003Inventors: Masatada Horiuchi, Kazuhiro Ohnishi, Akio Shima, Takashi Takahama, Masakazu Kawano
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Publication number: 20030207544Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.Type: ApplicationFiled: June 13, 2003Publication date: November 6, 2003Inventors: Hiromi Shimamoto, Takashi Uchino, Takeo Shiba, Kazuhiro Ohnishi, Yoichi Tamaki, Takashi Kobayashi, Toshiyuki Kikuchi, Takahide Ikeda
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Patent number: 6610569Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the polycrystalline first silicon layer has a positive in temperature dependence of resist while the second polycrystalline layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.Type: GrantFiled: August 28, 2000Date of Patent: August 26, 2003Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Hiromi Shimamoto, Takashi Uchino, Takeo Shiba, Kazuhiro Ohnishi, Yoichi Tamaki, Takashi Kobayashi, Toshiyuki Kikuchi, Takahide Ikeda
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Publication number: 20030094627Abstract: Provided is a manufacturing method of a semiconductor device which comprises forming, all over the surface of a substrate below the channel region of a MISFET, a p type impurity layer having a first peak in impurity concentration distribution and another p type impurity layer having a second peak in impurity concentration distribution, each layer having a function of preventing punch-through. Compared with a device having a punch through stopper layer of a pocket structure, the device of the present invention is suppressed in fluctuations in the threshold voltage. Moreover, with a relative increase in the controllable width of a depletion layer, a sub-threshold swing becomes small, thereby making it possible to prevent lowering of the threshold voltage and to improve a switching rate of the MISFET.Type: ApplicationFiled: November 19, 2002Publication date: May 22, 2003Inventors: Fumio Ootsuka, Takahiro Onai, Kazuhiro Ohnishi, Shoji Wakahara