Patents by Inventor Kazuhiro Yamamori

Kazuhiro Yamamori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8039970
    Abstract: A stacked semiconductor device includes a first semiconductor element mounted on a circuit substrate and a second semiconductor element stacked on the first semiconductor element via a spacer layer. An electrode pad of the first semiconductor element is electrically connected to a connection portion of the circuit substrate through a first metal wire. A vicinity of the end portion of the first metal wire connected to the electrode pad is in contact with an insulating protection film which covers the surface of the first semiconductor element.
    Type: Grant
    Filed: January 29, 2008
    Date of Patent: October 18, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiro Yamamori, Katsuhiro Ishida
  • Patent number: 7569921
    Abstract: A semiconductor device has a plurality of bare chips stacked on at least one of first and second main surfaces oppositely arranged on a support substrate, spacers arranged between two bare chips arranged adjacently in up and down direction among the plurality of bare chips, and inner leads which are arranged at both sides in a horizontal direction of the support substrate and are connected to pads of the bare chips via bonding wires, wherein the bonding wires which connect the pads of the bare chips at one end side of the spacers to the corresponding inner leads, are arranged not to contact the bare chip at the other end side of the same spacer.
    Type: Grant
    Filed: April 6, 2006
    Date of Patent: August 4, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Noboru Okane, Ryoji Matsushima, Kazuhiro Yamamori, Junya Sagara, Yoshio Iizuka, Kuniyuki Ohnishi
  • Publication number: 20080179757
    Abstract: A stacked semiconductor device includes a first semiconductor element mounted on a circuit substrate and a second semiconductor element stacked on the first semiconductor element via a spacer layer. An electrode pad of the first semiconductor element is electrically connected to a connection portion of the circuit substrate through a first metal wire. A vicinity of the end portion of the first metal wire connected to the electrode pad is in contact with an insulating protection film which covers the surface of the first semiconductor element.
    Type: Application
    Filed: January 29, 2008
    Publication date: July 31, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuhiro YAMAMORI, Katsuhiro Ishida
  • Publication number: 20070023922
    Abstract: A semiconductor package includes a circuit board having connection pads formed on a front and back surfaces, and a wiring network connected to these connection pads, as a package base. Metal bumps connected to at least part of the connection pads on the front and back surfaces via the wiring network are formed on the back surface of the circuit board as external connection terminals. One or a plurality of semiconductor elements electrically connected to the connection pad on the front surface side is or are mounted on a first element mounting part provided on the front surface side of the circuit board. One or plurality of semiconductor elements electrically connected to the connection pad on the back surface side is or are mounted on a second element mounting part provided on the back surface side of the circuit board.
    Type: Application
    Filed: July 21, 2006
    Publication date: February 1, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Noboru Okane, Ryoji Matsushima, Kazuhiro Yamamori, Junya Sagara, Yoshio Iizuka, Kuniyuki Oonishi
  • Publication number: 20070023875
    Abstract: A semiconductor package includes a lead frame having an element mounting part and a lead part. A first semiconductor element and a second semiconductor element are sequentially stacked on a principal surface at least on one side of the element mounting part. An insulating resin layer serving as a second adhesive layer is filled between the first semiconductor element and the second semiconductor element. An element-side end portion of a first bonding wire connected to the first semiconductor element is buried in the insulating resin layer.
    Type: Application
    Filed: July 21, 2006
    Publication date: February 1, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Noboru Okane, Ryoji Matsushima, Kazuhiro Yamamori, Junya Sagara, Yoshio Iizuka, Kuniyuki Oonishi, Atsushi Yoshimura
  • Publication number: 20060232288
    Abstract: A semiconductor device has a plurality of bare chips stacked on at least one of first and second main surfaces oppositely arranged on a support substrate, spacers arranged between two bare chips arranged adjacently in up and down direction among the plurality of bare chips, and inner leads which are arranged at both sides in a horizontal direction of the support substrate and are connected to pads of the bare chips via bonding wires, wherein the bonding wires which connect the pads of the bare chips at one end side of the spacers to the corresponding inner leads, are arranged not to contact the bare chip at the other end side of the same spacer.
    Type: Application
    Filed: April 6, 2006
    Publication date: October 19, 2006
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Noboru Okane, Ryoji Matsushima, Kazuhiro Yamamori, Junya Sagara, Yoshio Iizuka, Kuniyuki Ohnishi
  • Patent number: 5292050
    Abstract: A wire bonder comprises a pattern recognition mechanism. The pattern recognition mechanism includes a TV camera head, a camera control unit, a program research unit, and a bonder controller. The bonder controller includes a microcomputer, a control circuit, and a servo drive unit. The TV camera head and camera control unit detect locations of a first bonding pad formed on a first semiconductor chip and a second bonding pad formed on a second semiconductor chip. The program research unit calculates amounts of shift of the detected locations of the first and second bonding pads from reference locations thereof. The microcomputer corrects locations of first and second bonding points and those of first and second cutting points in accordance with the calculated amounts of shift. The control circuit and servo drive unit control the first and second bonding points and the first and second cutting points based on the corrected locations.
    Type: Grant
    Filed: December 3, 1992
    Date of Patent: March 8, 1994
    Assignee: Kabushuki Kaisha Toshiba
    Inventors: Tetsuya Nagaoka, Kazuhiro Yamamori