Abstract: Provided is a secure computation device for computing a comparison operation to two integers without the use of AND/XOR. The secure computation device compares a first integer a and a second integer b when the first integer a and the second integer b, which are 0 or greater and less than 2{circumflex over (?)}k (k being an integer of 1 or greater), are subjected to ring sharing. The secure computation device includes: an addition/subtraction circuitry; a bit decomposition circuitry; and a bit extraction circuitry. The addition/subtraction circuitry uses the first integer a, the second integer b, and 2{circumflex over (?)}k to carry out a predetermined addition or subtraction with ring sharing, and output an added/subtracted result. The bit decomposition circuitry converts the added/subtracted result to bit sharing, and outputs a bit shared result. The bit extraction circuitry extracts a (k+1)-th bit of the bit shared result, and outputs an extracted result.

Abstract: A collation apparatus 1 includes: a vector-type arithmetic unit 2 that calculates first similarity degrees using first feature points extracted from a target biological image and second feature points in a plurality of registered biological images, and narrows down the registered biological images based on the calculated first similarity degrees; and an arithmetic unit 3, other than the vector-type arithmetic unit 2, that calculates second similarity degrees using third feature points extracted from the target biological image and fourth feature points in the registered biological images obtained by the narrowing-down, and specifies a registered biological image based on the calculated second similarity degrees.

Abstract: Provided is a secure computation device for computing a comparison operation to two integers without the use of AND/XOR. The secure computation device compares a first integer a and a second integer b when the first integer a and the second integer b, which are 0 or greater and less than 2{circumflex over (?)}k (k being an integer of 1 or greater), are subjected to ring sharing. The secure computation device includes: an addition/subtraction circuitry; a bit decomposition circuitry; and a bit extraction circuitry. The addition/subtraction circuitry uses the first integer a, the second integer b, and 2{circumflex over (?)}k to carry out a predetermined addition or subtraction with ring sharing, and output an added/subtracted result. The bit decomposition circuitry converts the added/subtracted result to bit sharing, and outputs a bit shared result. The bit extraction circuitry extracts a (k+1)-th bit of the bit shared result, and outputs an extracted result.

Abstract: Matching processing between pieces of vector data is accelerated. A matching device 100 performs, for a plurality of pieces of vector data each having a plurality of dimensions, a predetermined operation pertaining to each dimension of each piece of vector data. The matching device 100 includes a collective operation unit 150 and an individual operation unit 160. The collective operation unit 150 performs the predetermined operation pertaining to a specific dimension among the plurality of dimensions by a vector operation for different pieces of vector data in the plurality of pieces of vector data. The individual operation unit 160 performs the predetermined operation pertaining to each dimension other than the specific dimension for a piece of vector data that satisfies a predetermined condition among the plurality of pieces of vector data.

Abstract: Matching processing between pieces of vector data is accelerated. A matching device 100 performs, for a plurality of pieces of vector data each having a plurality of dimensions, a predetermined operation pertaining to each dimension of each piece of vector data. The matching device 100 includes a collective operation unit 150 and an individual operation unit 160. The collective operation unit 150 performs the predetermined operation pertaining to a specific dimension among the plurality of dimensions by a vector operation for different pieces of vector data in the plurality of pieces of vector data. The individual operation unit 160 performs the predetermined operation pertaining to each dimension other than the specific dimension for a piece of vector data that satisfies a predetermined condition among the plurality of pieces of vector data.

Abstract: [Problem] To provide a data transfer device that efficiently reduces the transfer of data that does not need to be transferred. [Solution] This data transmission device is provided with: a memory; a processor that carries out writing to the memory; detection means for detecting the writing to the memory and identifiably detecting an update range, which is the range of the memory in which the writing is detected; extraction means for extracting, in response to receiving from the processor a transfer command specifying a transfer range in the memory, a range of the received transfer range included in the update range, as a transfer execution range; and transfer means for performing a data transfer that transfers to a transfer-destination node data stored in the transfer execution range of the memory.

Abstract: A computer system 10 includes a host means 110, an extension means 120 to extend functionality of the host means 110, and a common communication means 130 having a function of passing data. The host means 110 includes a storage means 111 and a processing means 112, the storage means 111 storing data and the processing means 112 processing the stored data. The extension means 120 is connected to the host means 110 to extend functionality of the host means 110, the extension means 120 including a storage means 121 and a processing means 122, the storage means 121 storing data and the processing means 122 processing the stored data. The common communication means 130 has a function of passing data between threads in the host means 110. The common communication means 130 has a function of passing data between a thread in the host means 110 and a thread in the extension means 120.

Abstract: A parameter determination unit 110 substitutes, for each of a plurality of applications, a recommended amount of resources and a quality of experience corresponding to the recommended amount of resources, and a minimum amount of resources and a quality of experience corresponding to the minimum amount of resources into a quality function f in expression (1) indicating a relation between an amount of resources R and a quality of experience Q, to determine parameters a and b. A resource amount determination unit 120 determines an amount of resources to be allocated to the plurality of applications using the quality function f for each application in which the parameters a and b are determined. The quality function f(x) is a monotonically increasing function having an inverse function f?1, connects (??,0) and (+?,1), and is symmetrical with respect to x=0.

Abstract: To reduce performance degradation due to a high-performance core's waiting for a processing result of a low-performance core in a multi-core processor including a plurality of cores with different running performance, included are a task pool that stores executable tasks for each computational core, a task scheduler, and a reference count analysis module that acquires hint information and a reference count estimation method from a running task and estimates a reference count of a task to be newly inserted into the task pool or a task existing in the task pool based on the specified method. The scheduler performs insertion and acquisition of a task by mainly using performance of the cores and the reference count.

Abstract: In a multi-core processor system, cache memories are provided respectively for a plurality of processors. An assignment management unit manages assignment of tasks to the processors. A cache status calculation unit calculates a cache usage status such as a memory access count and a cache hit ratio, with respect to each task. A first processor handles a plurality of first tasks that belong to a first process. If computation amount of the first process exceeds a predetermined threshold value, the assignment management unit refers to the cache usage status to preferentially select, as a migration target task, one of the plurality of first tasks whose memory access count is smaller or whose cache hit ratio is higher. Then, the assignment management unit newly assigns the migration target task to a second processor handling another process different from the first processor.

Abstract: A cache memory includes: a plurality of MSHRs (Miss Status/Information Holding Registers); a memory access identification unit that identifies a memory access included in an accepted memory access request; and a memory access association unit that associates a given memory access with the MSHR that is used when the memory access turns out to be a cache miss and determines, on the basis of the association, a candidate for the MSHR that is used by the memory access identified by the access identification unit.

Abstract: Provided is a computing resource allocation device capable of allocating computing resources to accommodate changing activity patterns. The device is equipped with an external environment recognition means that analyzes input values from sensors to specify the current environment, a memory means that stores a table in which the sensors required to specify the environment are correlated, a transition frequency computation means that computes the transition frequency at which a transition is made from an environment to another environment, and a computing resource allocation means that computes the amount of allocation of the computing resources to be used for the analysis based on the current environment by referencing the table and the transition frequency, and that allocates the computing resources for the analysis.

Abstract: A parameter determination unit 110 substitutes, for each of a plurality of applications, a recommended amount of resources and a quality of experience corresponding to the recommended amount of resources, and a minimum amount of resources and a quality of experience corresponding to the minimum amount of resources into a quality function fin expression (1) indicating a relation between an amount of resources R and a quality of experience Q, to determine parameters a and b. A resource amount determination unit 120 determines an amount of resources to be allocated to the plurality of applications using the quality function f for each application in which the parameters a and b are determined. The quality function f(x) is a monotonically increasing function having an inverse function f?1, connects (??) and (+?), and is symmetrical with respect to x=0. Q=f(x)=f((R?a)/b) ??(1).

Abstract: In a multi-core processor system, cache memories are provided respectively for a plurality of processors. An assignment management unit manages assignment of tasks to the processors. A cache status calculation unit calculates a cache usage status such as a memory access count and a cache hit ratio, with respect to each task. A first processor handles a plurality of first tasks that belong to a first process. If computation amount of the first process exceeds a predetermined threshold value, the assignment management unit refers to the cache usage status to preferentially select, as a migration target task, one of the plurality of first tasks whose memory access count is smaller or whose cache hit ratio is higher. Then, the assignment management unit newly assigns the migration target task to a second processor handling another process different from the first processor.

Abstract: To reduce performance degradation due to a high-performance core's waiting for a processing result of a low-performance core in a multi-core processor including a plurality of cores with different running performance, included are a task pool that stores executable tasks for each computational core, a task scheduler, and a reference count analysis module that acquires hint information and a reference count estimation method from a running task and estimates a reference count of a task to be newly inserted into the task pool or a task existing in the task pool based on the specified method. The scheduler performs insertion and acquisition of a task by mainly using performance of the cores and the reference count.

Abstract: Provided is a computing resource allocation device capable of allocating computing resources to accommodate changing activity patterns. The device is equipped with an external environment recognition means that analyzes input values from sensors to specify the current environment, a memory means that stores a table in which the sensors required to specify the environment are correlated, a transition frequency computation means that computes the transition frequency at which a transition is made from an environment to another environment, and a computing resource allocation means that computes the amount of allocation of the computing resources to be used for the analysis based on the current environment by referencing the table and the transition frequency, and that allocates the computing resources for the analysis.

Abstract: A cache memory includes: a plurality of MSHRs (Miss Status/Information Holding Registers); a memory access identification unit that identifies a memory access included in an accepted memory access request; and a memory access association unit that associates a given memory access with the MSHR that is used when the memory access turns out to be a cache miss and determines, on the basis of the association, a candidate for the MSHR that is used by the memory access identified by the access identification unit.