Patents by Inventor Kazuhisa Ishizaka

Kazuhisa Ishizaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10459902
    Abstract: Matching processing between pieces of vector data is accelerated. A matching device 100 performs, for a plurality of pieces of vector data each having a plurality of dimensions, a predetermined operation pertaining to each dimension of each piece of vector data. The matching device 100 includes a collective operation unit 150 and an individual operation unit 160. The collective operation unit 150 performs the predetermined operation pertaining to a specific dimension among the plurality of dimensions by a vector operation for different pieces of vector data in the plurality of pieces of vector data. The individual operation unit 160 performs the predetermined operation pertaining to each dimension other than the specific dimension for a piece of vector data that satisfies a predetermined condition among the plurality of pieces of vector data.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: October 29, 2019
    Assignee: NEC CORPORATION
    Inventor: Kazuhisa Ishizaka
  • Publication number: 20170199907
    Abstract: Matching processing between pieces of vector data is accelerated. A matching device 100 performs, for a plurality of pieces of vector data each having a plurality of dimensions, a predetermined operation pertaining to each dimension of each piece of vector data. The matching device 100 includes a collective operation unit 150 and an individual operation unit 160. The collective operation unit 150 performs the predetermined operation pertaining to a specific dimension among the plurality of dimensions by a vector operation for different pieces of vector data in the plurality of pieces of vector data. The individual operation unit 160 performs the predetermined operation pertaining to each dimension other than the specific dimension for a piece of vector data that satisfies a predetermined condition among the plurality of pieces of vector data.
    Type: Application
    Filed: June 11, 2015
    Publication date: July 13, 2017
    Applicant: NEC Corporation
    Inventor: Kazuhisa Ishizaka
  • Publication number: 20150319246
    Abstract: [Problem] To provide a data transfer device that efficiently reduces the transfer of data that does not need to be transferred. [Solution] This data transmission device is provided with: a memory; a processor that carries out writing to the memory; detection means for detecting the writing to the memory and identifiably detecting an update range, which is the range of the memory in which the writing is detected; extraction means for extracting, in response to receiving from the processor a transfer command specifying a transfer range in the memory, a range of the received transfer range included in the update range, as a transfer execution range; and transfer means for performing a data transfer that transfers to a transfer-destination node data stored in the transfer execution range of the memory.
    Type: Application
    Filed: December 5, 2013
    Publication date: November 5, 2015
    Inventor: Kazuhisa ISHIZAKA
  • Publication number: 20150032922
    Abstract: A computer system 10 includes a host means 110, an extension means 120 to extend functionality of the host means 110, and a common communication means 130 having a function of passing data. The host means 110 includes a storage means 111 and a processing means 112, the storage means 111 storing data and the processing means 112 processing the stored data. The extension means 120 is connected to the host means 110 to extend functionality of the host means 110, the extension means 120 including a storage means 121 and a processing means 122, the storage means 121 storing data and the processing means 122 processing the stored data. The common communication means 130 has a function of passing data between threads in the host means 110. The common communication means 130 has a function of passing data between a thread in the host means 110 and a thread in the extension means 120.
    Type: Application
    Filed: December 21, 2012
    Publication date: January 29, 2015
    Applicant: NEC CORPORATION
    Inventor: Kazuhisa Ishizaka
  • Patent number: 8938740
    Abstract: A parameter determination unit 110 substitutes, for each of a plurality of applications, a recommended amount of resources and a quality of experience corresponding to the recommended amount of resources, and a minimum amount of resources and a quality of experience corresponding to the minimum amount of resources into a quality function f in expression (1) indicating a relation between an amount of resources R and a quality of experience Q, to determine parameters a and b. A resource amount determination unit 120 determines an amount of resources to be allocated to the plurality of applications using the quality function f for each application in which the parameters a and b are determined. The quality function f(x) is a monotonically increasing function having an inverse function f?1, connects (??,0) and (+?,1), and is symmetrical with respect to x=0.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: January 20, 2015
    Assignee: NEC Corporation
    Inventors: Kosuke Nishihara, Kazuhisa Ishizaka
  • Patent number: 8897372
    Abstract: To reduce performance degradation due to a high-performance core's waiting for a processing result of a low-performance core in a multi-core processor including a plurality of cores with different running performance, included are a task pool that stores executable tasks for each computational core, a task scheduler, and a reference count analysis module that acquires hint information and a reference count estimation method from a running task and estimates a reference count of a task to be newly inserted into the task pool or a task existing in the task pool based on the specified method. The scheduler performs insertion and acquisition of a task by mainly using performance of the cores and the reference count.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: November 25, 2014
    Assignee: NEC Corporation
    Inventors: Kosuke Nishihara, Kazuhisa Ishizaka
  • Patent number: 8635405
    Abstract: In a multi-core processor system, cache memories are provided respectively for a plurality of processors. An assignment management unit manages assignment of tasks to the processors. A cache status calculation unit calculates a cache usage status such as a memory access count and a cache hit ratio, with respect to each task. A first processor handles a plurality of first tasks that belong to a first process. If computation amount of the first process exceeds a predetermined threshold value, the assignment management unit refers to the cache usage status to preferentially select, as a migration target task, one of the plurality of first tasks whose memory access count is smaller or whose cache hit ratio is higher. Then, the assignment management unit newly assigns the migration target task to a second processor handling another process different from the first processor.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: January 21, 2014
    Assignee: NEC Corporation
    Inventors: Kosuke Nishihara, Kazuhisa Ishizaka
  • Patent number: 8555001
    Abstract: A cache memory includes: a plurality of MSHRs (Miss Status/Information Holding Registers); a memory access identification unit that identifies a memory access included in an accepted memory access request; and a memory access association unit that associates a given memory access with the MSHR that is used when the memory access turns out to be a cache miss and determines, on the basis of the association, a candidate for the MSHR that is used by the memory access identified by the access identification unit.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: October 8, 2013
    Assignee: NEC Corporation
    Inventors: Kazuhisa Ishizaka, Takashi Miyazaki
  • Patent number: 8533726
    Abstract: Provided is a computing resource allocation device capable of allocating computing resources to accommodate changing activity patterns. The device is equipped with an external environment recognition means that analyzes input values from sensors to specify the current environment, a memory means that stores a table in which the sensors required to specify the environment are correlated, a transition frequency computation means that computes the transition frequency at which a transition is made from an environment to another environment, and a computing resource allocation means that computes the amount of allocation of the computing resources to be used for the analysis based on the current environment by referencing the table and the transition frequency, and that allocates the computing resources for the analysis.
    Type: Grant
    Filed: February 16, 2010
    Date of Patent: September 10, 2013
    Assignee: NEC Corporation
    Inventors: Kosuke Nishihara, Kazuhisa Ishizaka
  • Publication number: 20120324469
    Abstract: A parameter determination unit 110 substitutes, for each of a plurality of applications, a recommended amount of resources and a quality of experience corresponding to the recommended amount of resources, and a minimum amount of resources and a quality of experience corresponding to the minimum amount of resources into a quality function fin expression (1) indicating a relation between an amount of resources R and a quality of experience Q, to determine parameters a and b. A resource amount determination unit 120 determines an amount of resources to be allocated to the plurality of applications using the quality function f for each application in which the parameters a and b are determined. The quality function f(x) is a monotonically increasing function having an inverse function f?1, connects (??) and (+?), and is symmetrical with respect to x=0. Q=f(x)=f((R?a)/b) ??(1).
    Type: Application
    Filed: December 9, 2010
    Publication date: December 20, 2012
    Applicant: NEC CORPORATION
    Inventors: Kosuke Nishihara, Kazuhisa Ishizaka
  • Publication number: 20110314225
    Abstract: In a multi-core processor system, cache memories are provided respectively for a plurality of processors. An assignment management unit manages assignment of tasks to the processors. A cache status calculation unit calculates a cache usage status such as a memory access count and a cache hit ratio, with respect to each task. A first processor handles a plurality of first tasks that belong to a first process. If computation amount of the first process exceeds a predetermined threshold value, the assignment management unit refers to the cache usage status to preferentially select, as a migration target task, one of the plurality of first tasks whose memory access count is smaller or whose cache hit ratio is higher. Then, the assignment management unit newly assigns the migration target task to a second processor handling another process different from the first processor.
    Type: Application
    Filed: February 12, 2010
    Publication date: December 22, 2011
    Inventors: Kosuke Nishihara, Kazuhisa Ishizaka
  • Publication number: 20110310977
    Abstract: To reduce performance degradation due to a high-performance core's waiting for a processing result of a low-performance core in a multi-core processor including a plurality of cores with different running performance, included are a task pool that stores executable tasks for each computational core, a task scheduler, and a reference count analysis module that acquires hint information and a reference count estimation method from a running task and estimates a reference count of a task to be newly inserted into the task pool or a task existing in the task pool based on the specified method. The scheduler performs insertion and acquisition of a task by mainly using performance of the cores and the reference count.
    Type: Application
    Filed: January 22, 2010
    Publication date: December 22, 2011
    Inventors: Kosuke Nishihara, Kazuhisa Ishizaka
  • Publication number: 20110276980
    Abstract: Provided is a computing resource allocation device capable of allocating computing resources to accommodate changing activity patterns. The device is equipped with an external environment recognition means that analyzes input values from sensors to specify the current environment, a memory means that stores a table in which the sensors required to specify the environment are correlated, a transition frequency computation means that computes the transition frequency at which a transition is made from an environment to another environment, and a computing resource allocation means that computes the amount of allocation of the computing resources to be used for the analysis based on the current environment by referencing the table and the transition frequency, and that allocates the computing resources for the analysis.
    Type: Application
    Filed: February 16, 2010
    Publication date: November 10, 2011
    Applicant: NEC CORPORATION
    Inventors: Kosuke Nishihara, Kazuhisa Ishizaka
  • Publication number: 20110153950
    Abstract: A cache memory includes: a plurality of MSHRs (Miss Status/Information Holding Registers); a memory access identification unit that identifies a memory access included in an accepted memory access request; and a memory access association unit that associates a given memory access with the MSHR that is used when the memory access turns out to be a cache miss and determines, on the basis of the association, a candidate for the MSHR that is used by the memory access identified by the access identification unit.
    Type: Application
    Filed: July 23, 2009
    Publication date: June 23, 2011
    Inventors: Kazuhisa Ishizaka, Takashi Miyazaki