Patents by Inventor Kazuhito Yasue

Kazuhito Yasue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6873621
    Abstract: A system for controlling a bandwidth when receiving and reassembling a consecutive data stream transferred while segmented by AAL1 format cells which enables correct determination of non-P and P formats and reassembly of cells even when error arises in multiple bits including the CSI bit of an AAL1 cell or when adding dummy cells and thereby enabling prevention of a gap in data in a frame, comprising, in a data reassembly unit which reassembles received cells, an 8-cell buffer for storing 8 cells of a cycle of a sequence count (SC) of 0 to 7 and sending the cells out to a later stage after a check unit of a sequence number (SN) field confirms normalcy of the cells and a control unit for control so that the number of P format cells stored in the 8-cell buffer becomes 1 cell when 8 cells are stored in the 8-cell buffer.
    Type: Grant
    Filed: January 12, 2001
    Date of Patent: March 29, 2005
    Assignee: Fujitsu Limited
    Inventors: Jyoei Kamoi, Yoshihiro Uchida, Naoki Aihara, Mikio Nakayama, Kazuhito Yasue, Kazuhiko Kumagai
  • Publication number: 20040028041
    Abstract: In a packet processing device for controlling a band of a packet, a preprocessor assigns a time stamp to a received packet, and a shared resource portion performs a band control of packets based on reception order information (e.g. time stamp, sequence No.) of the packets distributed to distributed processors.
    Type: Application
    Filed: January 9, 2003
    Publication date: February 12, 2004
    Inventor: Kazuhito Yasue
  • Patent number: 6611409
    Abstract: The present invention relates to a line module protection method and a device utilizing that method. According to the line module protection method of the present invention, line module protection is performed by switching the connection from a broken line accommodating module to an auxiliary module. A plurality of line accommodating modules are included in a line accommodating unit connected to the lines in a network. The plurality of line accommodating modules are divided into a plurality of groups, and the auxiliary module is placed substantially at the same distance from all the groups. Thus, a large number of line accommodating modules for performing line module protection can be employed with one auxiliary module.
    Type: Grant
    Filed: July 10, 2000
    Date of Patent: August 26, 2003
    Assignee: Fujitsu Limited
    Inventors: Kazuhito Yasue, Mikio Nakayama, Takashi Nara
  • Publication number: 20020093949
    Abstract: A SOH (101) of a transmission frame of SDH (SONET) is terminated at a sender-side transmitter (3 or 4) and is added to remaining data at a receiver-side transmitter (4 or 3). At the sender-side transmitter (3 or 4), the remaining data (102, 103), including an administrative unit pointer (102) is converted into ATM cells and the ATM cells are sent out to an ATM network (2). After that, at the receiver-side transmitter (4 or 3), the remaining data is restored from the received ATM cells. As a result, operation, administration, and maintenance are independently performed over sections disposed at the input and the output sides of the ATM network (2). Further, processes (conversion to ATM cells, restoring SDH frames) are performed irrespective of the difference between the administrative pointer (102) and a payload (103), and the number of the signal paths (104) multiplexed in the payload (103).
    Type: Application
    Filed: February 25, 2002
    Publication date: July 18, 2002
    Inventors: Kazuhito Yasue, Mikio Makayama, Yoshihiro Uchida, Naoki Aihara, Jyoei Kamoi
  • Publication number: 20010017858
    Abstract: A system for controlling a bandwidth when receiving and reassembling a consecutive data stream transferred while segmented by AAL1 format cells which enables correct determination of non-P and P formats and reassembly of cells even when error arises in multiple bits including the CSI bit of an AAL1 cell or when adding dummy cells and thereby enabling prevention of a gap in data in a frame, comprising, in a data reassembly unit which reassembles received cells, an 8-cell buffer for storing 8 cells of a cycle of a sequence count (SC) of 0 to 7 and sending the cells out to a later stage after a check unit of a sequence number (SN) field confirms normalcy of the cells and a control unit for control so that the number of P format cells stored in the 8-cell buffer becomes 1 cell when 8 cells are stored in the 8-cell buffer.
    Type: Application
    Filed: January 12, 2001
    Publication date: August 30, 2001
    Applicant: Fujitsu Limited
    Inventors: Jyoei Kamoi, Yoshihiro Uchida, Naoki Aihara, Mikio Nakayama, Kazuhito Yasue, Kazuhiko Kumagai