Patents by Inventor Kazuki KAJITANI

Kazuki KAJITANI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INDEX VALUE ESTIMATION DEVICE, ESTIMATION SYSTEM, INDEX VALUE ESTIMATION METHOD, AND RECORDING MEDIUM
    Publication number: 20240122531
    Abstract: An index value estimation device including a data acquisition unit that acquires feature amount data including a feature amount extracted from sensor data related to a motion of a foot of a user and used for estimating an index value indicating a knee state of the user, a storage unit that stores an estimation model that outputs an index value according to an input of the feature amount data, an estimation unit that estimates an output obtained by inputting the acquired feature amount data to the estimation model as an index value indicating the knee state of the user, and an output unit that outputs information about the estimated index value indicating the knee state of the user.
    Type: Application
    Filed: December 26, 2023
    Publication date: April 18, 2024
    Applicant: NEC Corporation
    Inventors: Kazuki IHARA, Kenichiro FUKUSHI, Zhenwei WANG, Chenhui HUANG, Hiroshi KAJITANI, Fumiyuki NIHEY, Yoshitaka NOZAKI, Kentaro NAKAHARA
  • Three-dimensional memory device containing multi-threshold-voltage drain select gates and method of making the same
    Patent number: 10347647
    Abstract: A memory device contains a stack of insulating layers and electrically conductive word line layers, at least one first drain select gate electrode located over the stack and extending through a first drain select transistor and a second drain select transistor, at least one second drain select gate electrode located between the first drain select electrode and the stack, and extending through a third drain select transistor and a fourth drain select transistor. The first drain select transistor and the third drain select transistor are located in a first NAND memory string. The second drain select transistor and the fourth drain select transistor are located in a second NAND memory string different from the first NAND memory string. The first drain select transistor has a higher threshold voltage than the second drain select transistor. The third drain select transistor has a lower threshold voltage than the fourth drain select transistor.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: July 9, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Naohiro Hosoda, Keisuke Shigemura, Junichi Ariyoshi, Kazuki Kajitani, Yuji Fukano
  • THREE-DIMENSIONAL MEMORY DEVICE CONTAINING MULTI-THRESHOLD-VOLTAGE DRAIN SELECT GATES AND METHOD OF MAKING THE SAME
    Publication number: 20190198515
    Abstract: A memory device contains a stack of insulating layers and electrically conductive word line layers, at least one first drain select gate electrode located over the stack and extending through a first drain select transistor and a second drain select transistor, at least one second drain select gate electrode located between the first drain select electrode and the stack, and extending through a third drain select transistor and a fourth drain select transistor. The first drain select transistor and the third drain select transistor are located in a first NAND memory string. The second drain select transistor and the fourth drain select transistor are located in a second NAND memory string different from the first NAND memory string. The first drain select transistor has a higher threshold voltage than the second drain select transistor. The third drain select transistor has a lower threshold voltage than the fourth drain select transistor.
    Type: Application
    Filed: December 21, 2017
    Publication date: June 27, 2019
    Inventors: Naohiro HOSODA, Keisuke SHIGEMURA, Junichi ARIYOSHI, Kazuki KAJITANI, Yuji FUKANO