Patents by Inventor Kazuki Ota

Kazuki Ota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210286275
    Abstract: A detection apparatus detects an orientation reference of an object to be detected which includes an edge including the orientation reference. The apparatus includes a first detection system configured to detect the edge such that the orientation reference is detected, and a second detection system configured to detect, by projecting a pattern to a surface of the object and detecting an image formed by reflected light from the surface, a position of the surface in a direction perpendicular to the surface. After a focusing operation of the first detection system is performed based on the position of the surface detected by the second detection system, the first detection system detects the orientation reference.
    Type: Application
    Filed: March 8, 2021
    Publication date: September 16, 2021
    Inventors: Kazuki Ota, Hironori Maeda
  • Patent number: 11111566
    Abstract: The steel pipe of the present invention is a low alloy high strength seamless steel pipe for oil country tubular goods including a composition containing, in terms of mass %, C: 0.23 to 0.27%, Si: 0.01 to 0.35%, Mn: 0.45 to 0.70%, P: 0.010% or less, S: 0.001% or less, O: 0.0015% or less, Al: 0.015 to 0.080%, Cu: 0.02 to 0.09%, Cr: 0.8 to 1.5%, Mo: 0.5 to 1.0%, Nb: 0.02 to 0.05%, B: 0.0015 to 0.0030%, Ti: 0.005 to 0.020%, and N: 0.005% or less, and having a ratio of the Ti content to the N content (Ti/N) of 3.0 to 4.0, with the balance being Fe and inevitable impurities, the steel pipe having a ratio of a stress at a strain of 0.7% to a stress at a strain of 0.4% in a stress-strain curve of 1.02 or less and a yield strength of 655 MPa or more.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: September 7, 2021
    Assignee: JFE Steel Corporation
    Inventors: Mitsuhiro Okatsu, Masao Yuga, Hiroki Ota, Kazuki Fujimura
  • Publication number: 20210269666
    Abstract: An actinic energy ray-curable composition contains a low-refractive-index material capable of dissolving in a general-purpose solvent and that can impart excellent scratch resistance to a surface of its cured coating film, and a cured film and an antireflection film thereof. An actinic energy ray-curable composition contains a poly(perfluoroalkylene ether) chain-containing actinic energy ray-curable polyfunctional compound (I) and an actinic energy ray-curable compound (II) that is a copolymer of polymerizable unsaturated monomers, the actinic energy ray-curable compound (II) having a side chain containing a fluorinated alkyl group (x) having 1 to 6 carbon atoms to which a fluorine atom is attached and a side chain containing an actinic energy ray-curable group (y), the actinic energy ray-curable compound (II) having a silicone chain (z) with a molecular weight of 2,000 or more at one end of the copolymer, and a cured film and an antireflection film obtained by curing the composition.
    Type: Application
    Filed: June 25, 2019
    Publication date: September 2, 2021
    Applicant: DIC Corporation
    Inventors: Miki Ota, Ryosuke Hashide, Kazuki Obi, Nobuyuki Koike, Kenji Sakai
  • Publication number: 20210047727
    Abstract: A method of forming a metal-containing nitride film containing silicon includes: supplying a metal-containing gas into a processing container in which a substrate is accommodated; supplying a silicon-containing gas into the processing container; and supplying a nitrogen-containing gas into the processing container, wherein a series of processes, in which the supplying the metal-containing gas and the supplying the silicon-containing gas are executed n times in this order (where n is an integer of one or more) and then the supplying the nitrogen-containing gas is executed, is repeated m times in this order (where m is an integer of one or more).
    Type: Application
    Filed: August 10, 2020
    Publication date: February 18, 2021
    Inventors: Taichi MONDEN, Tetsu ZENKO, Kazuki OTA
  • Patent number: 10519902
    Abstract: A first downstream part of an intake manifold has a first downstream passage configured to communicate with an intake port of a first cylinder head. A second downstream part of the intake manifold has a second downstream passage configured to communicate with an intake port of a second cylinder head. An upstream part is coupled to the first downstream part and the second downstream part. The upstream part is arranged upstream from the first and second downstream parts in the flow direction of intake air and has a first upstream passage and a second upstream passage. The material of the first downstream part and the material of the second downstream part both have higher rigidity than the material of the upstream part.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: December 31, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Masato Fukui, Kazuki Ota
  • Publication number: 20190093609
    Abstract: A first downstream part of an intake manifold has a first downstream passage configured to communicate with an intake port of a first cylinder head. A second downstream part of the intake manifold has a second downstream passage configured to communicate with an intake port of a second cylinder head. An upstream part is coupled to the first downstream part and the second downstream part. The upstream part is arranged upstream from the first and second downstream parts in the flow direction of intake air and has a first upstream passage and a second upstream passage. The material of the first downstream part and the material of the second downstream part both have higher rigidity than the material of the upstream part.
    Type: Application
    Filed: August 20, 2018
    Publication date: March 28, 2019
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Masato FUKUI, Kazuki OTA
  • Publication number: 20180233590
    Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer).
    Type: Application
    Filed: March 16, 2018
    Publication date: August 16, 2018
    Inventors: Takashi Inoue, Tatsuo Nakayama, Yuji Ando, Yasuhiro Murase, Kazuki Ota, Hironobu Miyamoto, Katsumi Yamanoguchi, Naotaka Kuroda, Akio Wakejima, Yasuhiro Okamoto
  • Patent number: 9972207
    Abstract: An information collection system includes a first communication device provided at a first vehicle including a processor configured to execute a process. The process includes receiving operations by a first input section, and wirelessly transmitting, by a first transmission section, specific information according to the operation received by the first input section. The information collection system further includes a second communication device provided at a second vehicle including a processor configured to execute a process. The process includes receiving, by a first reception section, the specific information transmitted by the first transmission section, and wirelessly transmitting, to a device that is different from the first communication device by a second transmission section, position information enabling identification of a position at which the specific information was received by the first reception section.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: May 15, 2018
    Assignee: FUJITSU ADVANCED ENGINEERING LIMITED
    Inventors: Yoshitoshi Kurose, Kazuki Ota, Ryutaro Motora, Shota Irie, Tomomi Nishida
  • Patent number: 9954087
    Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer).
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: April 24, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Inoue, Tatsuo Nakayama, Yuji Ando, Yasuhiro Murase, Kazuki Ota, Hironobu Miyamoto, Katsumi Yamanoguchi, Naotaka Kuroda, Akio Wakejima, Yasuhiro Okamoto
  • Patent number: 9780738
    Abstract: A semiconductor device is provided with: a field-effect transistor that has a source electrode and a drain electrode that are connected to a semiconductor layer, a gate electrode that is provided on the surface of the semiconductor layer between the source electrode and the drain electrode, and a field plate electrode that is provided on the surface of the semiconductor layer in the vicinity of the gate electrode via an insulating layer, wherein the field-effect transistor amplifies high frequency signals received by the gate electrode to be outputted from the drain electrode; and a voltage dividing circuit that divides a potential difference between the drain electrode and a reference potential GND, and applies a bias voltage such that respective parts of the field plate electrode have a mutually equal potential.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: October 3, 2017
    Assignee: Renesas Electronics Corporation
    Inventor: Kazuki Ota
  • Patent number: 9768257
    Abstract: A high electron mobility transistor having a channel layer, electron supply layer, source electrode, and drain electrode is included so as to have a cap layer formed on the electron supply layer between the source and drain electrodes and having an inclined side surface, an insulating film having an opening portion on the upper surface of the cap layer and covering the side surface thereof, and a gate electrode is formed in the opening portion and extending, via the insulating film, over the side surface of the cap layer on the drain electrode side. The gate electrode having an overhang on the drain electrode side can reduce the peak electric field.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: September 19, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuki Ota, Yuji Ando
  • Patent number: 9582528
    Abstract: A system and method for operating a big-data platform that includes at a data analysis platform, receiving discrete client data; storing the client data in a network accessible distributed storage system that includes: storing the client data in a real-time storage system; and merging the client data into a columnar-based distributed archive storage system; receiving a data query request through a query interface; and selectively interfacing with the client data from the real-time storage system and archive storage system according to the query.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: February 28, 2017
    Assignee: Treasure Data, Inc.
    Inventors: Sadayuki Furuhashi, Hironobu Yoshikawa, Kazuki Ota
  • Patent number: 9530879
    Abstract: A semiconductor device including a field effect transistor including a substrate, a lower barrier layer provided on the substrate, a channel layer provided on the lower barrier layer, an electron supplying layer provided on the channel layer, a source electrode and a drain electrode provided on the electron layer, and a gate electrode provided between the source electrode and the drain electrode. The lower barrier layer includes a composition of In1-zAlzN (0?z?1). The channel layer includes a composition of AlxGa1-xN (0?x?1). A recess is provided in a region between the source electrode and the drain electrode, wherein the recess goes through the electron supplying layer to a depth that exposes the channel layer, and the gate electrode is disposed on a gate insulating film that covers a bottom surface and an inner wall surface of the recess.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: December 27, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuhiro Okamoto, Yuji Ando, Tatsuo Nakayama, Takashi Inoue, Kazuki Ota
  • Publication number: 20160284216
    Abstract: An information collection system includes a first communication device provided at a first vehicle including a processor configured to execute a process. The process includes receiving operations by a first input section, and wirelessly transmitting, by a first transmission section, specific information according to the operation received by the first input section. The information collection system further includes a second communication device provided at a second vehicle including a processor configured to execute a process. The process includes receiving, by a first reception section, the specific information transmitted by the first transmission section, and wirelessly transmitting, to a device that is different from the first communication device by a second transmission section, position information enabling identification of a position at which the specific information was received by the first reception section.
    Type: Application
    Filed: March 25, 2016
    Publication date: September 29, 2016
    Inventors: Yoshitoshi KUROSE, Kazuki OTA, Ryutaro MOTORA, Shota IRIE, Tomomi NISHIDA
  • Publication number: 20160246824
    Abstract: A system and method for operating a big-data platform that includes at a data analysis platform, receiving discrete client data; storing the client data in a network accessible distributed storage system that includes: storing the client data in a real-time storage system; and merging the client data into a columnar-based distributed archive storage system; receiving a data query request through a query interface; and selectively interfacing with the client data from the real-time storage system and archive storage system according to the query.
    Type: Application
    Filed: May 5, 2016
    Publication date: August 25, 2016
    Inventors: Sadayuki Furuhashi, Hironobu Yoshikawa, Kazuki Ota
  • Publication number: 20160079409
    Abstract: A semiconductor device including a field effect transistor including a substrate, a lower barrier layer provided on the substrate, a channel layer provided on the lower barrier layer, an electron supplying layer provided on the channel layer, a source electrode and a drain electrode provided on the electron layer, and a gate electrode provided between the source electrode and the drain electrode. The lower barrier layer includes a composition of In1-zAlzN (0?z?1). The channel layer includes a composition of AlxGa1-xN (0?x?1). A recess is provided in a region between the source electrode and the drain electrode, wherein the recess goes through the electron supplying layer to a depth that exposes the channel layer, and the gate electrode is disposed on a gate insulating film that covers a bottom surface and an inner wall surface of the recess.
    Type: Application
    Filed: November 20, 2015
    Publication date: March 17, 2016
    Applicant: Renesas Electronics Corporation
    Inventors: Yasuhiro OKAMOTO, Yuji ANDO, Tatsuo NAKAYAMA, Takashi INOUE, Kazuki OTA
  • Patent number: 9231096
    Abstract: A field effect transistor includes a substrate and a semiconductor layer provided on the substrate, wherein the semiconductor layer includes a lower barrier layer provided on the substrate, Ga-face grown, lattice relaxed, and having a composition In1?zAlzN (0?z?1), a channel layer having a composition of: AlxGa1?xN (0?x?1) or InyGa1?yN (0?y?1). Or GaN provided on and lattice-matched to the lower barrier layer, a source electrode and a drain electrode having ohmic contact to an upper part of the semiconductor layers, disposed spaced to each other, and a gate electrode arranged via a gate insulating film in a region lying between the source electrode and the drain electrode.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: January 5, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuhiro Okamoto, Yuji Ando, Tatsuo Nakayama, Takashi Inoue, Kazuki Ota
  • Publication number: 20150076511
    Abstract: A field effect transistor includes a substrate and a semiconductor layer provided on the substrate, wherein the semiconductor layer includes a lower barrier layer provided on the substrate, Ga-face grown, lattice relaxed, and having a composition In1?zAlzN (0?z?1), a channel layer having a composition of: AlxGa1?xN (0?x?1) or InyGa1?yN (0?y?1). Or GaN provided on and lattice-matched to the lower barrier layer, a source electrode and a drain electrode having ohmic contact to an upper part of the semiconductor layers, disposed spaced to each other, and a gate electrode arranged via a gate insulating film in a region lying between the source electrode and the drain electrode.
    Type: Application
    Filed: November 21, 2014
    Publication date: March 19, 2015
    Applicant: Renesas Electronics Corporation
    Inventors: Yasuhiro OKAMOTO, Yuji ANDO, Tatsuo NAKAYAMA, Takashi INOUE, Kazuki OTA
  • Patent number: 8981434
    Abstract: Provided is a semiconductor device in which the trade-off between the withstand voltage and the on-resistance is improved and the performance is increased. A semiconductor device comprises a substrate 1, a first n-type semiconductor layer 21?, a second n-type semiconductor layer 23, a p-type semiconductor layer 24, and a third n-type semiconductor layer 25?, wherein the first n-type semiconductor layer 21?, the second n-type semiconductor layer 23, the p-type semiconductor layer 24, and the third n-type semiconductor layer 25? are laminated at the upper side of the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 21? and the source electrode 12 is in ohmic-contact with the third n-type semiconductor layer 25?.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: March 17, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Hironobu Miyamoto, Yasuhiro Okamoto, Yuji Ando, Tatsuo Nakayama, Takashi Inoue, Kazuki Ota, Kazuomi Endo
  • Patent number: 8928038
    Abstract: A field effect transistor includes a substrate and a semiconductor layer provided on the substrate, wherein the semiconductor layer includes a lower barrier layer provided on the substrate, Ga-face grown, lattice relaxed, and having a composition In1-zAlzN (0?z?1), a channel layer having a composition of: AlxGa1-xN (0?x?1) or InyGa1-yN (0?y?1). Or GaN provided on and lattice-matched to the lower barrier layer, a source electrode and a drain electrode having ohmic contact to an upper part of the semiconductor layers, disposed spaced to each other, and a gate electrode arranged via a gate insulating film in a region lying between the source electrode and the drain electrode.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: January 6, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuhiro Okamoto, Yuji Ando, Tatsuo Nakayama, Takashi Inoue, Kazuki Ota