Patents by Inventor Kazuma Yoshida

Kazuma Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200365729
    Abstract: A semiconductor device includes a first transistor disposed in a first region of a semiconductor layer and a second transistor disposed in a second region of the semiconductor layer, and includes, on the surface of the semiconductor layer, first source pads, a first gate pad, second source pads, and a second gate pad. In the plan view of the semiconductor layer, the first and second transistors are aligned in a first direction; the first gate pad is disposed such that none of the first source pads is disposed between the first gate pad and a side parallel to the first direction and located closest to the first gate pad; and the second gate pad is disposed such that none of the second source pads is disposed between the second gate pad and a side parallel to the first direction and located closest to the second gate pad.
    Type: Application
    Filed: August 6, 2020
    Publication date: November 19, 2020
    Inventors: Ryosuke OKAWA, Toshikazu IMAI, Kazuma YOSHIDA, Tsubasa INOUE, Takeshi IMAMURA
  • Patent number: 10818006
    Abstract: A commodity monitoring device includes: an image acquisition unit (51) that sequentially acquires a sales floor image with the lapse of time; a shortage state detector (52) that detects a shortage state of commodities displayed on a sales floor based on the sales floor image, every time the image acquisition unit acquires the sales floor image; a duration acquisition unit (53) that acquires duration of the shortage state in a case where the shortage state of the commodities is detected by the shortage state detector; and a screen generator (54) that generates a state display image whose display form changes according to a length of the duration based on an output result of the duration acquisition unit to generate a monitoring screen including an image area in which the state display image is superimposed on the sales floor image.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: October 27, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yuichi Matsumoto, Kazuma Yoshida
  • Patent number: 10741545
    Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first body layer and a first connection part. The second transistor includes a second body layer and a second connection part. A second impedance, which is, in a path between the second connection part and the second body layer, inclusive, a maximum impedance seen by the first source electrode in the second body layer, is greater than a first impedance, which is, in a path between the first connection part and the first body layer, inclusive, a maximum impedance seen by the first source electrode in the first body layer.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: August 11, 2020
    Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
    Inventors: Masaki Tamaru, Kazuma Yoshida, Michiya Otsuji, Tetsuyuki Fukushima
  • Publication number: 20200236915
    Abstract: The present invention relates to a human artificial chromosome which is genetically transmissible to the next generation with high efficiency and the method for using the same. More specifically, the present invention relates to: a human artificial chromosome in which an about 3.5 Mb to about 1 Mb region containing an antibody ? light chain gene derived from human chromosome 22 is bound to a chromosome fragment which is transmissible to a progeny through a germ line of a non-human animal, said chromosome fragment is derived from another human chromosome; a non-human animal carrying the human artificial chromosome and an offspring thereof; a method for producing the non-human animal; a method for producing a human antibody using the nonhuman animal or an offspring thereof; and a human antibody-producing mouse carrying the human artificial chromosome.
    Type: Application
    Filed: September 12, 2019
    Publication date: July 30, 2020
    Inventors: Yoshimi KUROIWA, Kazuma TOMIZUKA, Hitoshi YOSHIDA, Isao ISHIDA
  • Publication number: 20200149631
    Abstract: When hydraulic information is not available for use, a lock mechanism control unit of a transmission's rotating shaft operated by hydraulic pressure sets the shift range to a non-running range and sets a parking lock to an unlocked state if a vehicle is in a running state and rotation speed of a drive unit is equal to or higher than a predetermined value, but sets the shift range to a parking range and sets the parking lock to a locked state if the vehicle is in a non-running state or the rotation speed is lower than the predetermined value.
    Type: Application
    Filed: October 28, 2019
    Publication date: May 14, 2020
    Inventors: Yuya Tachibanada, Kazuma Sasahara, Tetsuya Mochizuki, Koichi Fushimi, Hirotake Omoto, Shunsuke Yoshida
  • Patent number: 10636885
    Abstract: A semiconductor device includes a first gate electrode, a plurality of first source electrodes, a second gate electrode, and a plurality of second source electrodes. The first gate electrode is arranged with no other electrode between the first gate electrode and a first short side of the semiconductor substrate. The plurality of first source electrodes include a plurality of approximately rectangular first source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate. The second gate electrode is arranged with no other electrode between the second gate electrode and a second short side of the semiconductor substrate. The plurality of second source electrodes include a plurality of approximately rectangular second source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: April 28, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kazuma Yoshida, Takeshi Imamura, Toshikazu Imai, Ryosuke Okawa, Ryou Kato
  • Patent number: 10636906
    Abstract: A semiconductor device in chip size package includes first and second metal oxide semiconductor transistors both vertical transistors formed in first and second regions obtained by dividing the semiconductor device into halves. The first metal oxide semiconductor transistor includes one or more first gate electrodes and four or more first source electrodes provided in one major surface, each of the first gate electrodes is surrounded, in top view, by the first source electrodes, and for any combination of a first gate electrode and a first source electrode, closest points between the first gate and first source electrodes are on a line inclined to a chip side. The second metal oxide semiconductor transistor includes the same structure as the first metal oxide semiconductor transistor. A conductor that connects the drains of the first and second metal oxide semiconductor transistors is provided in the other major surface of the semiconductor device.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: April 28, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Tomonari Ota, Shigetoshi Sota, Eiji Yasuda, Takeshi Imamura, Toshikazu Imai, Ryosuke Okawa, Kazuma Yoshida, Masaaki Hirako, Dohwan Ahn
  • Publication number: 20200103241
    Abstract: An automobile operation control system is provided, which provides a service of a fixed-time and fixed-route operation and an on-demand operation using an operation vehicle to multiple users who reside in a given geographical area. The system includes an operation control device managed by an operation administrator and comprising a processor. The device is configured to receive a boarding reservation for the the on-demand operation from a first user of the multiple users. The devices suspends, in response to an acceptance of the reservation for the on-demand operation of which a second operation time window is within a given threshold from a first operation time window of the fixed-time fixed-route operation, the fixed-time and fixed-route operation scheduled to be operated in the first operation time window, when a given condition is satisfied.
    Type: Application
    Filed: September 18, 2019
    Publication date: April 2, 2020
    Inventors: Shinichiro Yoshida, Masashi Okamura, Yuki Okada, Kazuma Nishimura, Toshio Kamihachi
  • Patent number: 10607240
    Abstract: Position information on every moving object is acquired from a moving image of a monitoring area, and activity information during every unit time is acquired from the position information on every moving object. Conditions of an observation period of time are set according to a user input operation, the observation period of time is controlled in accordance with the conditions of the observation period of time, and the activity information during every unit time is aggregated during the observation period of time to acquire the activity information during the observation period of time. An activity map image is generated from the activity information during the observation period of time, and the activity map image and the moving image of the monitoring area are generated and output at every predetermined point in time.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: March 31, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yuichi Matsumoto, Kazuma Yoshida
  • Publication number: 20200066852
    Abstract: A semiconductor device includes a first gate electrode, a plurality of first source electrodes, a second gate electrode, and a plurality of second source electrodes. The first gate electrode is arranged with no other electrode between the first gate electrode and a first short side of the semiconductor substrate. The plurality of first source electrodes include a plurality of approximately rectangular first source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate. The second gate electrode is arranged with no other electrode between the second gate electrode and a second short side of the semiconductor substrate. The plurality of second source electrodes include a plurality of approximately rectangular second source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate.
    Type: Application
    Filed: October 31, 2019
    Publication date: February 27, 2020
    Inventors: Kazuma YOSHIDA, Takeshi IMAMURA, Toshikazu IMAI, Ryosuke OKAWA, Ryou KATO
  • Publication number: 20200035669
    Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first body layer and a first connection part. The second transistor includes a second body layer and a second connection part. A second impedance, which is, in a path between the second connection part and the second body layer, inclusive, a maximum impedance seen by the first source electrode in the second body layer, is greater than a first impedance, which is, in a path between the first connection part and the first body layer, inclusive, a maximum impedance seen by the first source electrode in the first body layer.
    Type: Application
    Filed: October 2, 2019
    Publication date: January 30, 2020
    Inventors: Masaki TAMARU, Kazuma YOSHIDA, Michiya OTSUJI, Tetsuyuki FUKUSHIMA
  • Patent number: 10541310
    Abstract: A semiconductor device includes a first gate electrode, a plurality of first source electrodes, a second gate electrode, and a plurality of second source electrodes. The first gate electrode is arranged with no other electrode between the first gate electrode and a first short side of the semiconductor substrate. The plurality of first source electrodes include a plurality of approximately rectangular first source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate. The second gate electrode is arranged with no other electrode between the second gate electrode and a second short side of the semiconductor substrate. The plurality of second source electrodes include a plurality of approximately rectangular second source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: January 21, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kazuma Yoshida, Takeshi Imamura, Toshikazu Imai, Ryosuke Okawa, Ryou Kato
  • Patent number: 10535143
    Abstract: A monitoring device includes a masking invalid region setter that sets a masking invalid region in video of a monitoring area in accordance with a manipulation input of a user, a moving object detector that detects a moving object from the video of the monitoring area and acquires region information for each moving object, a process target selector that selects whether or not to set an image region of a moving object detected by the moving object detector as a target of the masking process in accordance with whether or not the image region is positioned in the masking invalid region, and a video output controller that generates and outputs an output video in which the masking process is implemented only on an image region of a moving object set as a target of the masking process by the process target selector.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: January 14, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yuichi Matsumoto, Kazuma Yoshida
  • Publication number: 20190326601
    Abstract: To provide a negative electrode of a lithium ion battery excellent in cycle life characteristics. The negative electrode for a lithium ion battery includes an Si-based material as an active material, wherein a skeleton-forming agent including a silicate having a siloxane bond or a phosphate having an aluminophosphate bond as an ingredient is present on the surface and inside of an active material layer, and the skeleton of the active material is formed with the skeleton-forming agent.
    Type: Application
    Filed: March 25, 2017
    Publication date: October 24, 2019
    Applicants: ATTACCATO Limited Liability Company, ATTACCATO Limited Liability Company
    Inventors: Taichi Sakamoto, Takashi Mukai, Yuta Ikeuchi, Naoto Yamashita, Daichi Iwanari, Kazuma Yoshida, Kazuyoshi Tanaka
  • Patent number: 10448622
    Abstract: The present invention relates to a human artificial chromosome which is genetically transmissible to the next generation with high efficiency and the method for using the same. More specifically, the present invention relates to: a human artificial chromosome in which an about 3.5 Mb to about 1 Mb region containing an antibody ? light chain gene derived from human chromosome 22 is bound to a chromosome fragment which is transmissible to a progeny through a germ line of a non-human animal, said chromosome fragment is derived from another human chromosome; a non-human animal carrying the human artificial chromosome and an offspring thereof; a method for producing the non-human animal; a method for producing a human antibody using the nonhuman animal or an offspring thereof; and a human antibody-producing mouse carrying the human artificial chromosome.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: October 22, 2019
    Assignees: E. R. Squibb & Sons, L.L.C., Kyowa Hakko Kirin Co., Ltd
    Inventors: Yoshimi Kuroiwa, Kazuma Tomizuka, Hitoshi Yoshida, Isao Ishida
  • Publication number: 20190319126
    Abstract: A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 ?m, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.
    Type: Application
    Filed: June 20, 2019
    Publication date: October 17, 2019
    Inventors: Yoshihiro MATSUSHIMA, Shigetoshi SOTA, Eiji YASUDA, Toshikazu IMAI, Ryosuke OKAWA, Kazuma YOSHIDA, Ryou KATO
  • Publication number: 20190273141
    Abstract: A semiconductor device includes a first gate electrode, a plurality of first source electrodes, a second gate electrode, and a plurality of second source electrodes. The first gate electrode is arranged with no other electrode between the first gate electrode and a first short side of the semiconductor substrate. The plurality of first source electrodes include a plurality of approximately rectangular first source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate. The second gate electrode is arranged with no other electrode between the second gate electrode and a second short side of the semiconductor substrate. The plurality of second source electrodes include a plurality of approximately rectangular second source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate.
    Type: Application
    Filed: May 21, 2019
    Publication date: September 5, 2019
    Inventors: Kazuma YOSHIDA, Takeshi IMAMURA, Toshikazu IMAI, Ryosuke OKAWA, Ryou KATO
  • Publication number: 20190229194
    Abstract: A semiconductor device includes a first gate electrode, a plurality of first source electrodes, a second gate electrode, and a plurality of second source electrodes. The first gate electrode is arranged with no other electrode between the first gate electrode and a first short side of the semiconductor substrate. The plurality of first source electrodes include a plurality of approximately rectangular first source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate. The second gate electrode is arranged with no other electrode between the second gate electrode and a second short side of the semiconductor substrate. The plurality of second source electrodes include a plurality of approximately rectangular second source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate.
    Type: Application
    Filed: September 28, 2018
    Publication date: July 25, 2019
    Inventors: Kazuma YOSHIDA, Takeshi IMAMURA, Toshikazu IMAI, Ryosuke OKAWA, Ryou KATO
  • Patent number: 10340347
    Abstract: A semiconductor device includes a first gate electrode, a plurality of first source electrodes, a second gate electrode, and a plurality of second source electrodes. The first gate electrode is arranged with no other electrode between the first gate electrode and a first short side of the semiconductor substrate. The plurality of first source electrodes include a plurality of approximately rectangular first source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate. The second gate electrode is arranged with no other electrode between the second gate electrode and a second short side of the semiconductor substrate. The plurality of second source electrodes include a plurality of approximately rectangular second source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: July 2, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kazuma Yoshida, Takeshi Imamura, Toshikazu Imai, Ryosuke Okawa, Ryou Kato
  • Publication number: 20190157403
    Abstract: A semiconductor device includes a semiconductor substrate including a first conductivity-type impurity, a low-concentration impurity layer including a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate, a backside electrode including a metal material, and first and second transistors in the low-concentration impurity layer. The first transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer, the second transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer. The semiconductor substrate serves as a common drain region of the transistors.
    Type: Application
    Filed: January 29, 2019
    Publication date: May 23, 2019
    Inventors: Eiji Yasuda, Toshikazu Imai, Ryosuke Okawa, Takeshi Imamura, Mitsuaki Sakamoto, Kazuma Yoshida, Masaaki Hirako, Yasuyuki Masumoto, Shigetoshi Sota, Tomonari Oota