Patents by Inventor Kazuma Yoshida
Kazuma Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10965913Abstract: A person is detected from a moving image of the monitoring area, and position information on the person is acquired. Temporal statistical processing is performed on the position information, statistical information relating to a staying situation of the person is acquired in accordance with setting of a target period of time for the statistical processing, and thus a heat map moving image is generated. Furthermore, a mask image corresponding to a person image area is generated at every predetermined point in time based on the position information on the person. A monitoring moving image that results from superimposing the heat map image and the mask image onto a background image is generated and is output at every predetermined point in time.Type: GrantFiled: July 30, 2015Date of Patent: March 30, 2021Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Yuichi Matsumoto, Kazuma Yoshida
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Publication number: 20210050444Abstract: A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 ?m, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.Type: ApplicationFiled: October 14, 2020Publication date: February 18, 2021Inventors: Yoshihiro MATSUSHIMA, Shigetoshi SOTA, Eiji YASUDA, Toshikazu IMAI, Ryosuke OKAWA, Kazuma YOSHIDA, Ryou KATO
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Publication number: 20210036113Abstract: A semiconductor device includes a semiconductor substrate including a first conductivity-type impurity, a low-concentration impurity layer including a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate, a backside electrode including a metal material, and first and second transistors in the low-concentration impurity layer. The first transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer, the second transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer. The semiconductor substrate serves as a common drain region of the transistors.Type: ApplicationFiled: October 20, 2020Publication date: February 4, 2021Inventors: Eiji YASUDA, Toshikazu IMAI, Ryosuke OKAWA, Takeshi IMAMURA, Mitsuaki SAKAMOTO, Kazuma YOSHIDA, Masaaki HIRAKO, Yasuyuki MASUMOTO, Shigetoshi SOTA, Tomonari OOTA
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Publication number: 20210036114Abstract: A semiconductor device includes a semiconductor substrate including a first conductivity-type impurity, a low-concentration impurity layer including a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate, a backside electrode including a metal material, and first and second transistors in the low-concentration impurity layer. The first transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer, the second transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer. The semiconductor substrate serves as a common drain region of the transistors.Type: ApplicationFiled: October 20, 2020Publication date: February 4, 2021Inventors: Eiji YASUDA, Toshikazu IMAI, Ryosuke OKAWA, Takeshi IMAMURA, Mitsuaki SAKAMOTO, Kazuma YOSHIDA, Masaaki HIRAKO, Yasuyuki MASUMOTO, Shigetoshi SOTA, Tomonari OOTA
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Publication number: 20200388609Abstract: Provided is a semiconductor device which is a facedown mounting, chip-size-package-type semiconductor device and includes: a transistor element including a first electrode, a second electrode, and a control electrode which controls a conduction state between the first electrode and the second electrode; a plurality of first resistor elements each including a first electrode and a second electrode, the first electrodes of the first resistor elements being electrically connected to the second electrode of the transistor element; one or more external resistance terminals to which the second electrodes of the plurality of first resistor elements are physically connected; a first external terminal electrically connected to the first electrode of the transistor element; and an external control terminal electrically connected to the control electrode.Type: ApplicationFiled: January 25, 2019Publication date: December 10, 2020Inventors: Kazuma YOSHIDA, Ryosuke OKAWA, Tsubasa INOUE
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Patent number: 10854744Abstract: A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 ?m, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.Type: GrantFiled: June 20, 2019Date of Patent: December 1, 2020Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.Inventors: Yoshihiro Matsushima, Shigetoshi Sota, Eiji Yasuda, Toshikazu Imai, Ryosuke Okawa, Kazuma Yoshida, Ryou Kato
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Publication number: 20200365729Abstract: A semiconductor device includes a first transistor disposed in a first region of a semiconductor layer and a second transistor disposed in a second region of the semiconductor layer, and includes, on the surface of the semiconductor layer, first source pads, a first gate pad, second source pads, and a second gate pad. In the plan view of the semiconductor layer, the first and second transistors are aligned in a first direction; the first gate pad is disposed such that none of the first source pads is disposed between the first gate pad and a side parallel to the first direction and located closest to the first gate pad; and the second gate pad is disposed such that none of the second source pads is disposed between the second gate pad and a side parallel to the first direction and located closest to the second gate pad.Type: ApplicationFiled: August 6, 2020Publication date: November 19, 2020Inventors: Ryosuke OKAWA, Toshikazu IMAI, Kazuma YOSHIDA, Tsubasa INOUE, Takeshi IMAMURA
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Patent number: 10818006Abstract: A commodity monitoring device includes: an image acquisition unit (51) that sequentially acquires a sales floor image with the lapse of time; a shortage state detector (52) that detects a shortage state of commodities displayed on a sales floor based on the sales floor image, every time the image acquisition unit acquires the sales floor image; a duration acquisition unit (53) that acquires duration of the shortage state in a case where the shortage state of the commodities is detected by the shortage state detector; and a screen generator (54) that generates a state display image whose display form changes according to a length of the duration based on an output result of the duration acquisition unit to generate a monitoring screen including an image area in which the state display image is superimposed on the sales floor image.Type: GrantFiled: February 15, 2017Date of Patent: October 27, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Yuichi Matsumoto, Kazuma Yoshida
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Patent number: 10741545Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first body layer and a first connection part. The second transistor includes a second body layer and a second connection part. A second impedance, which is, in a path between the second connection part and the second body layer, inclusive, a maximum impedance seen by the first source electrode in the second body layer, is greater than a first impedance, which is, in a path between the first connection part and the first body layer, inclusive, a maximum impedance seen by the first source electrode in the first body layer.Type: GrantFiled: October 2, 2019Date of Patent: August 11, 2020Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.Inventors: Masaki Tamaru, Kazuma Yoshida, Michiya Otsuji, Tetsuyuki Fukushima
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Patent number: 10636906Abstract: A semiconductor device in chip size package includes first and second metal oxide semiconductor transistors both vertical transistors formed in first and second regions obtained by dividing the semiconductor device into halves. The first metal oxide semiconductor transistor includes one or more first gate electrodes and four or more first source electrodes provided in one major surface, each of the first gate electrodes is surrounded, in top view, by the first source electrodes, and for any combination of a first gate electrode and a first source electrode, closest points between the first gate and first source electrodes are on a line inclined to a chip side. The second metal oxide semiconductor transistor includes the same structure as the first metal oxide semiconductor transistor. A conductor that connects the drains of the first and second metal oxide semiconductor transistors is provided in the other major surface of the semiconductor device.Type: GrantFiled: December 26, 2017Date of Patent: April 28, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Tomonari Ota, Shigetoshi Sota, Eiji Yasuda, Takeshi Imamura, Toshikazu Imai, Ryosuke Okawa, Kazuma Yoshida, Masaaki Hirako, Dohwan Ahn
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Patent number: 10636885Abstract: A semiconductor device includes a first gate electrode, a plurality of first source electrodes, a second gate electrode, and a plurality of second source electrodes. The first gate electrode is arranged with no other electrode between the first gate electrode and a first short side of the semiconductor substrate. The plurality of first source electrodes include a plurality of approximately rectangular first source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate. The second gate electrode is arranged with no other electrode between the second gate electrode and a second short side of the semiconductor substrate. The plurality of second source electrodes include a plurality of approximately rectangular second source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate.Type: GrantFiled: October 31, 2019Date of Patent: April 28, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Kazuma Yoshida, Takeshi Imamura, Toshikazu Imai, Ryosuke Okawa, Ryou Kato
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Patent number: 10607240Abstract: Position information on every moving object is acquired from a moving image of a monitoring area, and activity information during every unit time is acquired from the position information on every moving object. Conditions of an observation period of time are set according to a user input operation, the observation period of time is controlled in accordance with the conditions of the observation period of time, and the activity information during every unit time is aggregated during the observation period of time to acquire the activity information during the observation period of time. An activity map image is generated from the activity information during the observation period of time, and the activity map image and the moving image of the monitoring area are generated and output at every predetermined point in time.Type: GrantFiled: August 4, 2015Date of Patent: March 31, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Yuichi Matsumoto, Kazuma Yoshida
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Publication number: 20200066852Abstract: A semiconductor device includes a first gate electrode, a plurality of first source electrodes, a second gate electrode, and a plurality of second source electrodes. The first gate electrode is arranged with no other electrode between the first gate electrode and a first short side of the semiconductor substrate. The plurality of first source electrodes include a plurality of approximately rectangular first source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate. The second gate electrode is arranged with no other electrode between the second gate electrode and a second short side of the semiconductor substrate. The plurality of second source electrodes include a plurality of approximately rectangular second source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate.Type: ApplicationFiled: October 31, 2019Publication date: February 27, 2020Inventors: Kazuma YOSHIDA, Takeshi IMAMURA, Toshikazu IMAI, Ryosuke OKAWA, Ryou KATO
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Publication number: 20200035669Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first body layer and a first connection part. The second transistor includes a second body layer and a second connection part. A second impedance, which is, in a path between the second connection part and the second body layer, inclusive, a maximum impedance seen by the first source electrode in the second body layer, is greater than a first impedance, which is, in a path between the first connection part and the first body layer, inclusive, a maximum impedance seen by the first source electrode in the first body layer.Type: ApplicationFiled: October 2, 2019Publication date: January 30, 2020Inventors: Masaki TAMARU, Kazuma YOSHIDA, Michiya OTSUJI, Tetsuyuki FUKUSHIMA
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Patent number: 10541310Abstract: A semiconductor device includes a first gate electrode, a plurality of first source electrodes, a second gate electrode, and a plurality of second source electrodes. The first gate electrode is arranged with no other electrode between the first gate electrode and a first short side of the semiconductor substrate. The plurality of first source electrodes include a plurality of approximately rectangular first source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate. The second gate electrode is arranged with no other electrode between the second gate electrode and a second short side of the semiconductor substrate. The plurality of second source electrodes include a plurality of approximately rectangular second source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate.Type: GrantFiled: May 21, 2019Date of Patent: January 21, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Kazuma Yoshida, Takeshi Imamura, Toshikazu Imai, Ryosuke Okawa, Ryou Kato
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Patent number: 10535143Abstract: A monitoring device includes a masking invalid region setter that sets a masking invalid region in video of a monitoring area in accordance with a manipulation input of a user, a moving object detector that detects a moving object from the video of the monitoring area and acquires region information for each moving object, a process target selector that selects whether or not to set an image region of a moving object detected by the moving object detector as a target of the masking process in accordance with whether or not the image region is positioned in the masking invalid region, and a video output controller that generates and outputs an output video in which the masking process is implemented only on an image region of a moving object set as a target of the masking process by the process target selector.Type: GrantFiled: January 29, 2016Date of Patent: January 14, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Yuichi Matsumoto, Kazuma Yoshida
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Publication number: 20190326601Abstract: To provide a negative electrode of a lithium ion battery excellent in cycle life characteristics. The negative electrode for a lithium ion battery includes an Si-based material as an active material, wherein a skeleton-forming agent including a silicate having a siloxane bond or a phosphate having an aluminophosphate bond as an ingredient is present on the surface and inside of an active material layer, and the skeleton of the active material is formed with the skeleton-forming agent.Type: ApplicationFiled: March 25, 2017Publication date: October 24, 2019Applicants: ATTACCATO Limited Liability Company, ATTACCATO Limited Liability CompanyInventors: Taichi Sakamoto, Takashi Mukai, Yuta Ikeuchi, Naoto Yamashita, Daichi Iwanari, Kazuma Yoshida, Kazuyoshi Tanaka
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Publication number: 20190319126Abstract: A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 ?m, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.Type: ApplicationFiled: June 20, 2019Publication date: October 17, 2019Inventors: Yoshihiro MATSUSHIMA, Shigetoshi SOTA, Eiji YASUDA, Toshikazu IMAI, Ryosuke OKAWA, Kazuma YOSHIDA, Ryou KATO
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Publication number: 20190273141Abstract: A semiconductor device includes a first gate electrode, a plurality of first source electrodes, a second gate electrode, and a plurality of second source electrodes. The first gate electrode is arranged with no other electrode between the first gate electrode and a first short side of the semiconductor substrate. The plurality of first source electrodes include a plurality of approximately rectangular first source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate. The second gate electrode is arranged with no other electrode between the second gate electrode and a second short side of the semiconductor substrate. The plurality of second source electrodes include a plurality of approximately rectangular second source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate.Type: ApplicationFiled: May 21, 2019Publication date: September 5, 2019Inventors: Kazuma YOSHIDA, Takeshi IMAMURA, Toshikazu IMAI, Ryosuke OKAWA, Ryou KATO
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Publication number: 20190229194Abstract: A semiconductor device includes a first gate electrode, a plurality of first source electrodes, a second gate electrode, and a plurality of second source electrodes. The first gate electrode is arranged with no other electrode between the first gate electrode and a first short side of the semiconductor substrate. The plurality of first source electrodes include a plurality of approximately rectangular first source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate. The second gate electrode is arranged with no other electrode between the second gate electrode and a second short side of the semiconductor substrate. The plurality of second source electrodes include a plurality of approximately rectangular second source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate.Type: ApplicationFiled: September 28, 2018Publication date: July 25, 2019Inventors: Kazuma YOSHIDA, Takeshi IMAMURA, Toshikazu IMAI, Ryosuke OKAWA, Ryou KATO